From 9960ca010a78c8da4f62575b05594fa154180fff Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Jan 2015 12:36:45 +0100
Subject: [PATCH] test on hardware and clean up/fix

---
 README                            | 10 +++++++--
 litesata/frontend/bist.py         |  5 ++++-
 targets/bist.py                   |  3 +--
 test/{test_link.py => test_la.py} | 35 +++++++++++++++++--------------
 4 files changed, 32 insertions(+), 21 deletions(-)
 rename test/{test_link.py => test_la.py} (75%)

diff --git a/README b/README
index f93e35e0..901bb281 100644
--- a/README
+++ b/README
@@ -101,13 +101,19 @@ devel [AT] lists.m-labs.hk.
   git clone https://github.com/enjoy-digital/litesata
 
 6. Build and load BIST design (only for KC705 for now):
-  python3 make.py all
+  python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
 
 7. Test design (only for KC705 for now):
   go to ./test directory and run:
   python3 bist.py
 
-8. If you only want to build the core and use it with your
+8. Visualize Link Layer transactions (if BISTSoCDevel):
+  go to ./test directory and run:
+  python3 test_la.py [your_cond]
+  your_cond can be wr_cmd, id_cmd, rd_resp, ...
+  (open test_la.py to see all conditions or add yours)
+
+9. If you only want to build the core and use it with your
   regular design flow:
   python3 make.py -t core build-core
 
diff --git a/litesata/frontend/bist.py b/litesata/frontend/bist.py
index aa1dbdcd..cd405822 100644
--- a/litesata/frontend/bist.py
+++ b/litesata/frontend/bist.py
@@ -226,6 +226,7 @@ class LiteSATABISTIdentify(Module):
 		source, sink = user_port.sink, user_port.source
 
 		self.fsm = fsm = FSM(reset_state="IDLE")
+		self.submodules += fsm
 		fsm.act("IDLE",
 			self.done.eq(1),
 			If(self.start,
@@ -288,4 +289,6 @@ class LiteSATABIST(Module, AutoCSR):
 			generator = LiteSATABISTUnitCSR(generator)
 			checker = LiteSATABISTUnitCSR(checker)
 			identify = LiteSATABISTIdentifyCSR(identify)
-		self.submodules += generator, checker, identify
+		self.submodules.generator = generator
+		self.submodules.checker = checker
+		self.submodules.identify = identify
diff --git a/targets/bist.py b/targets/bist.py
index ba7bcf07..9d803149 100644
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -136,7 +136,6 @@ class BISTSoC(GenSoC, AutoCSR):
 		"sata":		10,
 	}
 	csr_map.update(GenSoC.csr_map)
-
 	def __init__(self, platform):
 		clk_freq = 166*1000000
 		GenSoC.__init__(self, platform, clk_freq)
@@ -152,7 +151,7 @@ class BISTSoC(GenSoC, AutoCSR):
 
 class BISTSoCDevel(BISTSoC, AutoCSR):
 	csr_map = {
-		"la":			10
+		"la":			20
 	}
 	csr_map.update(BISTSoC.csr_map)
 	def __init__(self, platform):
diff --git a/test/test_link.py b/test/test_la.py
similarity index 75%
rename from test/test_link.py
rename to test/test_la.py
index dfa7d4c5..436bc9e2 100644
--- a/test/test_link.py
+++ b/test/test_la.py
@@ -12,16 +12,26 @@ wb.open()
 regs = wb.regs
 ###
 
+trig = "now"
 if len(sys.argv) < 2:
-	print("Need trigger condition!")
-	sys.exit(0)
+	print("No trigger condition, triggering immediately!")
+else:
+	trig = sys.argv[1]
 
 conditions = {}
+conditions["now"] = {}
+conditions["id_cmd"] = {
+	"sata_command_tx_sink_stb"				: 1,
+	"sata_command_tx_sink_payload_identify"	: 1,
+}
+conditions["id_resp"] = {
+	"source_source_payload_data" : primitives["X_RDY"],
+}
 conditions["wr_cmd"] = {
 	"sata_command_tx_sink_stb"			: 1,
 	"sata_command_tx_sink_payload_write"	: 1,
 }
-conditions["wr_dma_activate"] = {
+conditions["wr_resp"] = {
 	"sata_command_rx_source_stb"			: 1,
 	"sata_command_rx_source_payload_write"	: 1,
 }
@@ -29,27 +39,20 @@ conditions["rd_cmd"] = {
 	"sata_command_tx_sink_stb"			: 1,
 	"sata_command_tx_sink_payload_read"	: 1,
 }
-conditions["rd_data"] = {
+conditions["rd_resp"] = {
 	"sata_command_rx_source_stb"			: 1,
 	"sata_command_rx_source_payload_read"	: 1,
 }
-conditions["id_cmd"] = {
-	"sata_command_tx_sink_stb"				: 1,
-	"sata_command_tx_sink_payload_identify"	: 1,
-}
-conditions["id_pio_setup"] = {
-	"source_source_payload_data" : primitives["X_RDY"],
-}
 
-la.prog_term(port=0, cond=conditions[sys.argv[1]])
+la.prog_term(port=0, cond=conditions[trig])
 la.prog_sum("term")
 
 # Trigger / wait / receive
-la.trigger(offset=512, length=2000)
+la.trigger(offset=64, length=1024)
 
-#identify.run()
-generator.run(0, 2, 1, 0)
-#checker.run(0, 2, 1, 0)
+#identify.run(blocking=False)
+generator.run(0, 2, 1, 0, blocking=False)
+#checker.run(0, 2, 1, 0, blocking=False)
 la.wait_done()
 
 la.read()
-- 
2.30.2