From 9961ed14d9908adf8cd3db5b109dd4fb4cfec1d5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 May 2020 20:53:13 +0100 Subject: [PATCH] comments --- src/soc/experiment/l0_cache.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index ca1a9636..e5ae956a 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -292,6 +292,7 @@ class L0CacheBuffer(Elaboratable): comb += wrport.en.eq(1) # enable write comb += reset_l.s.eq(1) # reset mode after 1 cycle + # after waiting one cycle (reset_l is "sync" mode), reset the port with m.If(reset_l.q): comb += idx_l.s.eq(1) # deactivate port-index selector comb += ld_active.r.eq(1) # leave the ST active for 1 cycle -- 2.30.2