From 9981b3d83bcc35c1aa47ecd25ed71ef484d776ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 May 2020 15:51:52 +0100 Subject: [PATCH] add progress counter --- src/ieee754/cordic/test/test_fp_pipe.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py index 56f853c7..ee18ff21 100644 --- a/src/ieee754/cordic/test/test_fp_pipe.py +++ b/src/ieee754/cordic/test/test_fp_pipe.py @@ -44,7 +44,12 @@ class SinCosTestCase(FHDLTestCase): for i in range(40): yield def reader_process(): + counter = 200 while True: + counter -= 1 + if counter == 0: # some indication of progress + print (".", sep="", end="", flush=True) + counter = 200 yield vld = yield dut.n.valid_o if vld: @@ -63,6 +68,8 @@ class SinCosTestCase(FHDLTestCase): except StopIteration: break + print() # newline after end of progress-indicator + sim.add_sync_process(writer_process) sim.add_sync_process(reader_process) with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[ -- 2.30.2