From 9995768e985c067badb94377180f7b0f60379d67 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Nov 2021 12:03:29 +0000 Subject: [PATCH] only check regs right at the end in test_core.py overlap mode --- src/soc/simple/test/test_core.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 0c1be141..cdc84482 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -216,6 +216,7 @@ class TestRunner(FHDLTestCase): imem_ifacetype='', addr_wid=48, mask_wid=8, + allow_overlap=True, reg_wid=64) cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE) @@ -307,12 +308,32 @@ class TestRunner(FHDLTestCase): # set operand and get inputs yield from wait_for_busy_clear(core) + # synchronised (non-overlap) is fine to check + if not core.allow_overlap: + # register check + yield from check_regs(self, sim, core, test, code) + + # Memory check + yield from check_mem(self, sim, core, test, code) + + # non-overlap mode is only fine to check right at the end + if core.allow_overlap: + # wait until all settled + # XXX really this should be in DMI, which should in turn + # use issuer.any_busy to not send back "stopped" signal + while (yield core.o.any_busy_o): + yield + # register check yield from check_regs(self, sim, core, test, code) # Memory check yield from check_mem(self, sim, core, test, code) + # give a couple extra clock cycles for gtkwave display to be happy + yield + yield + sim.add_sync_process(process) with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw", traces=[]): -- 2.30.2