From 999a2f612a566e63b675bb5ff1aa4be96c109a1c Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 3 Aug 2019 22:59:33 +0000 Subject: [PATCH] vendor.lattice_ice40: add missing signal indexing. --- nmigen/vendor/lattice_ice40.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index 74fc36f..6f1021a 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -278,8 +278,8 @@ class LatticeICE40Platform(TemplatedPlatform): elif pin.xdr == 2: # Re-register both inputs before they enter fabric. This increases hold time # to an entire cycle, and adds one cycle of latency. - io_args.append(("o", "D_IN_0", i0_ff)) - io_args.append(("o", "D_IN_1", i1_ff)) + io_args.append(("o", "D_IN_0", i0_ff[bit])) + io_args.append(("o", "D_IN_1", i1_ff[bit])) if "o" in pin.dir: if pin.xdr < 2: io_args.append(("i", "D_OUT_0", pin_o[bit])) @@ -287,7 +287,7 @@ class LatticeICE40Platform(TemplatedPlatform): # Re-register negedge output after it leaves fabric. This increases setup time # to an entire cycle, and doesn't add latency. io_args.append(("i", "D_OUT_0", pin_o0[bit])) - io_args.append(("i", "D_OUT_1", o1_ff)) + io_args.append(("i", "D_OUT_1", o1_ff[bit])) if pin.dir in ("oe", "io"): io_args.append(("i", "OUTPUT_ENABLE", pin.oe)) -- 2.30.2