From 999cc9a153214ef8371776ccce5b84dd50808999 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 7 Jan 2021 19:14:42 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index bdc1863e6..cfadc1a3d 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -366,7 +366,7 @@ but select different *bits* of the same CRs `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD). -Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". +Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs. # Extra Remapped Encoding -- 2.30.2