From 99b56c424146eac9fd784e5f659a3f1385fc98bf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 2 May 2018 09:44:52 +0100 Subject: [PATCH] add notes --- isa_conflict_resolution.mdwn | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/isa_conflict_resolution.mdwn b/isa_conflict_resolution.mdwn index 5a316988e..463a139d4 100644 --- a/isa_conflict_resolution.mdwn +++ b/isa_conflict_resolution.mdwn @@ -392,6 +392,27 @@ TBD: placeholder as of 26apr2018 > would solve that problem.  it could even be set to the foreign isa.  > which would be hilarious. +jacob's idea: one hart, one configuration: + +>>>  (a) RV-Base ISA, particularly code-execution in the critical S-mode +>>> trap-handling, is *EXTREMELY* unlikely to ever be changed, even +>>> thinking 30 years into the future ? +>> +>> Oddly enough, due to the minimalism of RISC-V, I believe that this is +>> actually quite likely.  :-) +>> +>>>  thus the hypothesis is that not only is it the common code-path to +>>> *not* switch the ISA in the S-mode trap but that the instructions used +>>> are extremely unlikely to be changed between "RV Base Revisions". +>>> +>> Correct.  I argue that S-mode should *not* be able to switch the selected +>> ISA on multi-arch processors.  +> +> that would produce an artificial limitation which would prevent +> and prohibit implementors from making a single-core (single-hart) +> multi-configuration processor. + + # Summary and Conclusion -- 2.30.2