From 99c534afdff4caca8700ae02e2c245084418209e Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 17 Aug 2022 14:21:18 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 5ae53b4a5..11ed17be9 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -77,9 +77,9 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: |sz |SNZ| 0 RG | 0 | dz / | normal mode | |sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce), SUBVL=1 | |zz |SNZ| 0 RG | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 0 RG | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | -|sz |SNZ| 0 RG | 1 | SVM 1 | Pack/Unpack mode, SUBVL>1 | -|sz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | +|zz |SNZ| 0 RG | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | +|zz |SNZ| 0 RG | 1 | SVM 1 | Pack/Unpack mode, SUBVL>1 | +|zz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | |sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | Fields: -- 2.30.2