From 99cf5b6d03171b50ecee780e143683141a1734a1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 May 2021 17:48:02 +0100 Subject: [PATCH] add beginning support for SVP64 IEEE754 FP --- openpower/isatables/LDSTRM-2P-1S1D.csv | 2 ++ openpower/isatables/LDSTRM-2P-1S2D.csv | 2 ++ openpower/isatables/LDSTRM-2P-2S.csv | 2 ++ openpower/isatables/LDSTRM-2P-2S1D.csv | 10 ++++++++++ openpower/isatables/LDSTRM-2P-3S.csv | 3 +++ openpower/isatables/RM-1P-3S1D.csv | 4 ---- openpower/isatables/RM-2P-1S1D.csv | 19 ++++++++++--------- src/openpower/decoder/power_svp64.py | 5 +++++ src/openpower/sv/trans/svp64.py | 4 ++-- 9 files changed, 36 insertions(+), 15 deletions(-) diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv index 4048d2f3..56addddc 100644 --- a/openpower/isatables/LDSTRM-2P-1S1D.csv +++ b/openpower/isatables/LDSTRM-2P-1S1D.csv @@ -3,5 +3,7 @@ lwz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lbz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lhz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lha,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 +lfs,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 +lfd,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 ld,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lwa,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv index 20435822..4e2f359e 100644 --- a/openpower/isatables/LDSTRM-2P-1S2D.csv +++ b/openpower/isatables/LDSTRM-2P-1S2D.csv @@ -3,4 +3,6 @@ lwzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lbzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhau,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA +lfsu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA +lfdu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA ldu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-2S.csv b/openpower/isatables/LDSTRM-2P-2S.csv index 3ba308ad..43577459 100644 --- a/openpower/isatables/LDSTRM-2P-2S.csv +++ b/openpower/isatables/LDSTRM-2P-2S.csv @@ -2,4 +2,6 @@ insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2 stw,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 stb,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 sth,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 +stfs,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 +stfd,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 std,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv index 5025c286..cd0a67ce 100644 --- a/openpower/isatables/LDSTRM-2P-2S1D.csv +++ b/openpower/isatables/LDSTRM-2P-2S1D.csv @@ -11,14 +11,20 @@ lwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 ldbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lwbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 +lfsx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 +lfdx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 lwzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lbzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 +lfiwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 ldcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 +lfiwzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 stwu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA stbu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA sthu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA +stfsu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA +stfdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA stdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA ldux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA @@ -26,7 +32,11 @@ lbzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA +lfsux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA +lfdux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA stdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA stwux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA stbux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA sthux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stfsux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA +stfdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv index 169fc276..c62488b3 100644 --- a/openpower/isatables/LDSTRM-2P-3S.csv +++ b/openpower/isatables/LDSTRM-2P-3S.csv @@ -5,10 +5,13 @@ stbx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stdbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stwbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 +stfsx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 +stfdx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stwcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stbcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 +stfiwx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stdcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stwcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 stdcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index 11db3631..9fbc3f0d 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -31,7 +31,3 @@ isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 -fmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 -fmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 -fnmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 -fnmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index ab3c77ca..0e8e79fb 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -34,33 +34,34 @@ addzeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 extsh,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 extsb,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 extsw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 -fcfid[u]s,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fsqrts,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fres,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 frsqrtes,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcfids,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcfidus,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fsqrt,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fre,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 frsqrte,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -18/7=mffsfamily,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +0/12=frsp,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +0/14=fctiw,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +0/15=fctiwz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 1/8=fneg,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 2/8=fmr,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 4/8=fnabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +4/14=fctiwu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +4/15=fctiwuz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 8/8=fabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 12/8=frin,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 13/8=friz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 14/8=frip,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 15/8=frim,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -0/12=frsp,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -0/14=fctiw,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -4/14=fctiwu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +18/7=mffs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 25/14=fctid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +25/15=fctidz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 26/14=fcfid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 29/14=fctidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -30/14=fcfidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -0/15=fctiwz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -4/15=fctiwuz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 -25/15=fctidz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 29/15=fctiduz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +30/14=fcfidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 addic.,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 rlwinm,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 andi.,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index 3e3332ea..0fa44901 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -15,6 +15,9 @@ def is_CR_5bit(regname): def is_GPR(regname): return regname in ['RA', 'RB', 'RC', 'RS', 'RT'] +def is_FPR(regname): + return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT'] + def get_regtype(regname): if is_CR_3bit(regname): return "CR_3bit" @@ -22,6 +25,8 @@ def get_regtype(regname): return "CR_5bit" if is_GPR(regname): return "GPR" + if is_FPR(regname): + return "FPR" def decode_extra(rm, prefix=''): diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index d9fb43ac..ef60dffa 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -266,8 +266,8 @@ class SVP64Asm: # XXX also TODO: the LD/ST modes which are different # https://libre-soc.org/openpower/sv/ldst/ - # encode SV-GPR field into extra, v3.0field - if rtype == 'GPR': + # encode SV-GPR and SV-FPR field into extra, v3.0field + if rtype in ['GPR', 'FPR']: sv_extra, field = get_extra_gpr(etype, regmode, field) # now sanity-check. EXTRA3 is ok, EXTRA2 has limits # (and shrink to a single bit if ok) -- 2.30.2