From 99dc9a997c606fe3ffb27cfe3f8afdb6fe751cf4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Dec 2021 00:44:48 +0000 Subject: [PATCH] link MSR.PR into MMU FSM OP_FETCH_FAILED --- src/soc/fu/mmu/fsm.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 5d0cc814..7f0b81b4 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -91,6 +91,7 @@ class FSMMMUStage(ControlBase): i_data, o_data = self.p.i_data, self.n.o_data op = i_data.ctx.op nia_i = op.nia + msr_i = op.msr a_i, b_i, spr1_i = i_data.ra, i_data.rb, i_data.spr1 o, exc_o, spr1_o = o_data.o, o_data.exception, o_data.spr1 @@ -223,6 +224,7 @@ class FSMMMUStage(ControlBase): # from accepting any other LD/ST requests. comb += valid.eq(1) # start "pulse" comb += ldst.instr_fault.eq(blip) + comb += ldst.priv_mode.eq(msr_i[MSR.PR]) comb += ldst.maddr.eq(nia_i) # XXX should not access this! mmu_done_delay = Signal() -- 2.30.2