From 99e01a66b4c619fb8c7d6f978038eb7a3661c160 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 30 Mar 2023 11:09:12 +0100 Subject: [PATCH] aarch64: Add the SME2 predicate-related instructions Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN[]. This is the first instance of a vector/predicate index having no suffix. --- gas/config/tc-aarch64.c | 85 +- gas/testsuite/gas/aarch64/illegal-sve2.l | 16 +- gas/testsuite/gas/aarch64/sme-9.d | 4 +- gas/testsuite/gas/aarch64/sme2-6-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-6-invalid.l | 139 ++ gas/testsuite/gas/aarch64/sme2-6-invalid.s | 92 + gas/testsuite/gas/aarch64/sme2-6-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-6-noarch.l | 145 ++ gas/testsuite/gas/aarch64/sme2-6.d | 153 ++ gas/testsuite/gas/aarch64/sme2-6.s | 164 ++ gas/testsuite/gas/aarch64/sme2-7-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-7-invalid.l | 20 + gas/testsuite/gas/aarch64/sme2-7-invalid.s | 14 + gas/testsuite/gas/aarch64/sme2-7-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-7-noarch.l | 321 +++ gas/testsuite/gas/aarch64/sme2-7.d | 329 +++ gas/testsuite/gas/aarch64/sme2-7.s | 351 ++++ .../gas/aarch64/sve2-sme2-1-invalid.l | 3 + .../gas/aarch64/sve2-sme2-1-invalid.s | 4 + .../gas/aarch64/sve2-sme2-2-invalid.d | 3 + .../gas/aarch64/sve2-sme2-2-invalid.l | 25 + .../gas/aarch64/sve2-sme2-2-invalid.s | 12 + .../gas/aarch64/sve2-sme2-2-noarch.d | 3 + .../gas/aarch64/sve2-sme2-2-noarch.l | 257 +++ gas/testsuite/gas/aarch64/sve2-sme2-2.d | 265 +++ gas/testsuite/gas/aarch64/sve2-sme2-2.s | 287 +++ include/opcode/aarch64.h | 11 + opcodes/aarch64-asm-2.c | 51 +- opcodes/aarch64-asm.c | 33 +- opcodes/aarch64-asm.h | 1 + opcodes/aarch64-dis-2.c | 1843 ++++++++++------- opcodes/aarch64-dis.c | 33 +- opcodes/aarch64-dis.h | 1 + opcodes/aarch64-opc-2.c | 10 + opcodes/aarch64-opc.c | 62 +- opcodes/aarch64-opc.h | 9 + opcodes/aarch64-tbl.h | 60 + 37 files changed, 3967 insertions(+), 851 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-6-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-6-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-6-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-6-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-6-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-6.d create mode 100644 gas/testsuite/gas/aarch64/sme2-6.s create mode 100644 gas/testsuite/gas/aarch64/sme2-7-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-7-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-7-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-7-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-7-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-7.d create mode 100644 gas/testsuite/gas/aarch64/sme2-7.s create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2.d create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index a61ad5dab15..a433925e320 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -474,6 +474,8 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen) PN is expected, and vice versa, so the issue at this point is "predicate-like" vs. "not predicate-like". */ return N_("expected an SVE predicate register at operand %d"); + if (mask == reg_type_masks[REG_TYPE_PN]) + return N_("expected an SVE predicate-as-counter register at operand %d"); if (mask == reg_type_masks[REG_TYPE_VZ]) return N_("expected a vector register at operand %d"); if (mask == reg_type_masks[REG_TYPE_ZP]) @@ -1277,7 +1279,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '[')) { /* Reject Sn[index] syntax. */ - if (!is_typed_vecreg) + if (reg->type != REG_TYPE_PN && !is_typed_vecreg) { first_error (_("this type of register can't be indexed")); return NULL; @@ -1344,6 +1346,14 @@ eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2) && e1.index == e2.index); } +/* Return the register number mask for registers of type REG_TYPE. */ + +static inline int +reg_type_mask (aarch64_reg_type reg_type) +{ + return reg_type == REG_TYPE_P ? 15 : 31; +} + /* This function parses a list of vector registers of type TYPE. On success, it returns the parsed register list information in the following encoded format: @@ -1372,7 +1382,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, char *str = *ccp; int nb_regs; struct vector_type_el typeinfo, typeinfo_first; - int val, val_range; + int val, val_range, mask; int in_range; int ret_val; bool error = false; @@ -1396,6 +1406,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, val = -1; val_range = -1; in_range = 0; + mask = reg_type_mask (type); do { if (in_range) @@ -1431,7 +1442,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, (_("invalid range in vector register list")); error = true; } - val_range = (val_range + 1) & 0x1f; + val_range = (val_range + 1) & mask; } else { @@ -1452,7 +1463,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, nb_regs++; if (val_range == val) break; - val_range = (val_range + 1) & 0x1f; + val_range = (val_range + 1) & mask; } in_range = 0; ptr_flags |= PTR_GOOD_MATCH; @@ -4316,8 +4327,10 @@ parse_adrp (char **str) /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array of SIZE tokens in which index I gives the token for field value I, - or is null if field value I is invalid. REG_TYPE says which register - names should be treated as registers rather than as symbolic immediates. + or is null if field value I is invalid. If the symbolic operand + can also be given as a 0-based integer, REG_TYPE says which register + names should be treated as registers rather than as symbolic immediates + while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise. Return true on success, moving *STR past the operand and storing the field value in *VAL. */ @@ -4345,6 +4358,9 @@ parse_enum_string (char **str, int64_t *val, const char *const *array, return true; } + if (reg_type == REG_TYPE_MAX) + return false; + if (!parse_immediate_expression (&p, &exp, reg_type)) return false; @@ -4971,6 +4987,12 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs) goto failure; \ } while (0) +#define po_strict_enum_or_fail(array) do { \ + if (!parse_enum_string (&str, &val, array, \ + ARRAY_SIZE (array), REG_TYPE_MAX)) \ + goto failure; \ + } while (0) + #define po_misc_or_fail(expr) do { \ if (!expr) \ goto failure; \ @@ -6445,16 +6467,18 @@ ldst_lo12_determine_real_reloc_type (void) return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz]; } -/* Check whether a register list REGINFO is valid. The registers must be - numbered in increasing order (modulo 32). They must also have a - consistent stride. +/* Check whether a register list REGINFO is valid. The registers have type + REG_TYPE and must be numbered in increasing order (modulo the register + bank size). They must have a consistent stride. Return true if the list is valid, describing it in LIST if so. */ static bool -reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list) +reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list, + aarch64_reg_type reg_type) { - uint32_t i, nb_regs, prev_regno, incr; + uint32_t i, nb_regs, prev_regno, incr, mask; + mask = reg_type_mask (reg_type); nb_regs = 1 + (reginfo & 0x3); reginfo >>= 2; @@ -6469,7 +6493,7 @@ reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list) uint32_t curr_regno, curr_incr; reginfo >>= 5; curr_regno = reginfo & 0x1f; - curr_incr = (curr_regno - prev_regno) & 0x1f; + curr_incr = (curr_regno - prev_regno) & mask; if (curr_incr == 0) return false; else if (i == 1) @@ -6638,7 +6662,9 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_PNg4_10: case AARCH64_OPND_SVE_PNn: case AARCH64_OPND_SVE_PNt: + case AARCH64_OPND_SME_PNd3: case AARCH64_OPND_SME_PNg3: + case AARCH64_OPND_SME_PNn: reg_type = REG_TYPE_PN; goto vector_reg; @@ -6723,6 +6749,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ZtxN: case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Zmx2: + case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx4: case AARCH64_OPND_SME_Ztx2_STRIDED: @@ -6730,6 +6758,11 @@ parse_operands (char *str, const aarch64_opcode *opcode) reg_type = REG_TYPE_Z; goto vector_reg_list; + case AARCH64_OPND_SME_Pdx2: + case AARCH64_OPND_SME_PdxN: + reg_type = REG_TYPE_P; + goto vector_reg_list; + case AARCH64_OPND_LVn: case AARCH64_OPND_LVt: case AARCH64_OPND_LVt_AL: @@ -6753,7 +6786,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) if (val == PARSE_FAIL) goto failure; - if (! reg_list_valid_p (val, &info->reglist)) + if (! reg_list_valid_p (val, &info->reglist, reg_type)) { set_fatal_syntax_error (_("invalid register list")); goto failure; @@ -6779,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; if (!(vectype.defined & NTA_HASTYPE)) { - if (reg_type == REG_TYPE_Z) + if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P) set_fatal_syntax_error (_("missing type suffix")); goto failure; } @@ -7707,6 +7740,24 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_PNn3_INDEX1: + case AARCH64_OPND_SME_PNn3_INDEX2: + reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype); + if (!reg) + goto failure; + if (!(vectype.defined & NTA_HASINDEX)) + { + set_syntax_error (_("missing register index")); + goto failure; + } + info->reglane.regno = reg->number; + info->reglane.index = vectype.index; + if (vectype.type == NT_invtype) + info->qualifier = AARCH64_OPND_QLF_NIL; + else + info->qualifier = vectype_to_qualifier (&vectype); + break; + case AARCH64_OPND_BTI_TARGET: val = parse_bti_operand (&str, &(info->hint_option)); if (val == PARSE_FAIL) @@ -7753,6 +7804,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->qualifier = qualifier; break; + case AARCH64_OPND_SME_VLxN_10: + case AARCH64_OPND_SME_VLxN_13: + po_strict_enum_or_fail (aarch64_sme_vlxn_array); + info->imm.value = val; + break; + case AARCH64_OPND_MOPS_ADDR_Rd: case AARCH64_OPND_MOPS_ADDR_Rs: po_char_or_fail ('['); diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index f07ef384f94..5f43b56df14 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -3139,7 +3139,7 @@ [^ :]+:[0-9]+: Info: other valid variant\(s\): [^ :]+:[0-9]+: Info: usubwt z0\.s, z0\.s, z0\.h [^ :]+:[0-9]+: Info: usubwt z0\.d, z0\.d, z0\.s -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,x0,x0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,x0,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x32,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0' @@ -3165,7 +3165,7 @@ [^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0 [^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0 [^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0 -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,w0,w0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,w0,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w32,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0' @@ -3177,7 +3177,7 @@ [^ :]+:[0-9]+: Info: whilege p0\.d, w0, w0 [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31' -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,x0,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x32,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0' @@ -3203,7 +3203,7 @@ [^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0 [^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0 [^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0 -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,w0,w0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,w0,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w32,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0' @@ -3215,7 +3215,7 @@ [^ :]+:[0-9]+: Info: whilegt p0\.d, w0, w0 [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31' -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,x0,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x32,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0' @@ -3241,7 +3241,7 @@ [^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0 [^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0 [^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0 -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,w0,w0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,w0,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w32,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0' @@ -3253,7 +3253,7 @@ [^ :]+:[0-9]+: Info: whilehi p0\.d, w0, w0 [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31' -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,x0,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x32,x0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0' @@ -3279,7 +3279,7 @@ [^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0 [^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0 [^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0 -[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,w0,w0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,w0,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w32,w0' [^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32' [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0' diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d index 9a6175c3906..69b27020d01 100644 --- a/gas/testsuite/gas/aarch64/sme-9.d +++ b/gas/testsuite/gas/aarch64/sme-9.d @@ -72,5 +72,5 @@ Disassembly of section \.text: f8: 25277c61 psel p1, p15, p3.b\[w15, 0\] fc: 252778a2 psel p2, p14, p5.b\[w15, 0\] 100: 25244200 \.inst 0x25244200 ; undefined - 104: 25244010 \.inst 0x25244010 ; undefined - 108: 25244210 \.inst 0x25244210 ; undefined + 104: 25244010 whilege pn8.b, x0, x4, vlx2 + 108: 25244210 whilege pn8.b, x16, x4, vlx2 diff --git a/gas/testsuite/gas/aarch64/sme2-6-invalid.d b/gas/testsuite/gas/aarch64/sme2-6-invalid.d new file mode 100644 index 00000000000..d3e9450a524 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-6-invalid.s +#error_output: sme2-6-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-6-invalid.l b/gas/testsuite/gas/aarch64/sme2-6-invalid.l new file mode 100644 index 00000000000..cac3ec4cfb7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6-invalid.l @@ -0,0 +1,139 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp 0,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,0,vlx2' +[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,0' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp xsp,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp sp,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: operand mismatch -- `cntp w0,pn0\.b,vlx2' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2 +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `cntp x0,p0\.b,vlx2' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,pn16\.b,vlx2' +[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,#0' +[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vl' +[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vlx3' +[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0,vlx2' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2 +[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0\.q,vlx2' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2 +[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2 +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `pext 0,pn8\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p0\.b,0' +[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `pext pn8\.b,pn0\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `pext z0\.b,pn8\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,z8\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,x8' +[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext p8\.b,p8\[0\]' +[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext p8\.b,pn8' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[4\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[1<<32\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.b,pn8\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\] +[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\] +[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.q,pn8\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\] +[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\] +[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\] +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pext {p0\.b-p2\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `pext {p0-p1},pn8\[0\]' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn7\[0\]' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn0\[0\]' +[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext {p0\.b-p1\.b},pn8' +[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext {p0\.b-p1\.b},p0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `pext {p0\.b-p1\.b},pn8\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: pext {p0\.b-p1\.b}, pn8\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: pext {p0\.h-p1\.h}, pn8\[0\] +[^ :]+:[0-9]+: Info: pext {p0\.s-p1\.s}, pn8\[0\] +[^ :]+:[0-9]+: Info: pext {p0\.d-p1\.d}, pn8\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[2\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[1<<32\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `ptrue 0' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.b' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.b' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.h' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.h' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.s' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.s' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.d' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.d' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `ptrue pn8\.b,all' +[^ :]+:[0-9]+: Error: operand mismatch -- `ptrue pn8\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: ptrue pn8\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: ptrue pn8\.h +[^ :]+:[0-9]+: Info: ptrue pn8\.s +[^ :]+:[0-9]+: Info: ptrue pn8\.d +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `sel 0,pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `sel {z0\.b-z1\.b},0,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected '{' at operand 3 -- `sel {z0\.b-z1\.b},pn8,0,{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected '{' at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `sel {z0\.b-z1\.b},p8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn7,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/z,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/m,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn0,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z11\.b-z12\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z17\.b-z18\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z4\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z10\.b-z13\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z15\.b-z18\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z1\.b-z4\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z22\.b-z25\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z27\.b-z30\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z5\.b-z8\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z14\.b-z17\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z19\.b-z22\.b}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z1\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z2\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z2\.b}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z2\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z2\.b}' +[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.q-z1\.q},pn8,{z0\.q-z1\.q},{z0\.q-z1\.q}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-6-invalid.s b/gas/testsuite/gas/aarch64/sme2-6-invalid.s new file mode 100644 index 00000000000..b94dcbab65f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6-invalid.s @@ -0,0 +1,92 @@ + cntp 0, pn0.b, vlx2 + cntp x0, 0, vlx2 + cntp x0, pn0.b, 0 + + cntp xsp, pn0.b, vlx2 + cntp sp, pn0.b, vlx2 + cntp w0, pn0.b, vlx2 + cntp x0, p0.b, vlx2 + cntp x0, pn16.b, vlx2 + cntp x0, pn0.b, #0 + cntp x0, pn0.b, vl + cntp x0, pn0.b, vlx3 + + cntp x0, pn0, vlx2 + cntp x0, pn0.q, vlx2 + + pext 0, pn8[0] + pext p0.b, 0 + + pext pn8.b, pn0[0] + pext z0.b, pn8[0] + pext p8.b, z8[0] + pext p8.b, x8 + pext p8.b, p8[0] + pext p8.b, pn8 + pext p8.b, pn8[-1] + pext p8.b, pn8[4] + pext p8.b, pn8[1 << 32] + pext p8.b, pn8.b[0] + pext p8.q, pn8[0] + + pext { p0.b - p2.b }, pn8[0] + pext { p0 - p1 }, pn8[0] + pext { p0.b - p1.b }, pn7[0] + pext { p0.b - p1.b }, pn0[0] + pext { p0.b - p1.b }, pn8 + pext { p0.b - p1.b }, p0[0] + pext { p0.b - p1.b }, pn8.b[0] + pext { p0.b - p1.b }, pn8[-1] + pext { p0.b - p1.b }, pn8[2] + pext { p0.b - p1.b }, pn8[1 << 32] + + ptrue 0 + + ptrue pn0.b + ptrue pn7.b + ptrue pn0.h + ptrue pn7.h + ptrue pn0.s + ptrue pn7.s + ptrue pn0.d + ptrue pn7.d + ptrue pn8.b, all + ptrue pn8.q + + sel 0, pn8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, 0, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, 0, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, 0 + + sel { z1.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, p8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn7, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8/z, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8/m, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn0, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z11.b - z12.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z17.b - z18.b } + + sel { z1.b - z4.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z10.b - z13.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z15.b - z18.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z1.b - z4.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z22.b - z25.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z27.b - z30.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z5.b - z8.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z14.b - z17.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z19.b - z22.b } + + sel { z0.b - z1.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z1.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z1.b } + + sel { z0.b - z2.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z2.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z2.b } + + sel { z0.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z0.b - z2.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z2.b } + + sel { z0.q - z1.q }, pn8, { z0.q - z1.q }, { z0.q - z1.q } diff --git a/gas/testsuite/gas/aarch64/sme2-6-noarch.d b/gas/testsuite/gas/aarch64/sme2-6-noarch.d new file mode 100644 index 00000000000..5a2f1a5a889 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-6.s +#error_output: sme2-6-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-6-noarch.l b/gas/testsuite/gas/aarch64/sme2-6-noarch.l new file mode 100644 index 00000000000..173e99a2b3e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6-noarch.l @@ -0,0 +1,145 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.B,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.b,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.b,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X11,PN13\.b,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.H,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.h,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.h,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.h,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X20,PN9\.h,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.s,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.s,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.s,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.s,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X15,PN8\.s,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.d,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.d,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.d,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.d,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `cntp X4,PN5\.d,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.B,PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.b,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p4\.b,pn11\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.H,PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.h,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p5\.h,pn14\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.S,PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.s,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p6\.s,pn10\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.D,PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.d,pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext p7\.d,pn9\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b,p1\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.B-P1\.B},PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.b-p15\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b,p0\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b-p0\.b},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p7\.b-p8\.b},pn12\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h,p1\.h},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.H-P1\.H},PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.h-p15\.h},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h,p0\.h},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h-p0\.h},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p2\.h-p3\.h},pn14\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s,p1\.s},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.S-P1\.S},PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.s-p15\.s},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s,p0\.s},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s-p0\.s},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p5\.s-p6\.s},pn13\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d,p1\.d},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.D-P1\.D},PN8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.d-p15\.d},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d,p0\.d},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d-p0\.d},pn8\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn15\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `pext {p12\.d-p13\.d},pn9\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn11\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn9\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn14\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn12\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.b-z31\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn15,{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z30\.b-z31\.b},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z30\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z2\.b-z3\.b},pn12,{z6\.b-z7\.b},{z10\.b-z11\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.h-z31\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn15,{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z12\.h-z13\.h},pn9,{z14\.h-z15\.h},{z16\.h-z17\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.s-z31\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn15,{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z18\.s-z19\.s},pn11,{z22\.s-z23\.s},{z24\.s-z25\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.d-z31\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn15,{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.d-z9\.d},pn14,{z26\.d-z27\.d},{z28\.d-z29\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.b-z31\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z28\.b-z31\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z28\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z4\.b-z7\.b},pn10,{z8\.b-z11\.b},{z12\.b-z15\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.h-z31\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.h-z11\.h},pn10,{z16\.h-z19\.h},{z20\.h-z23\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.s-z31\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z16\.s-z19\.s},pn10,{z20\.s-z23\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.d-z31\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sel {z20\.d-z23\.d},pn10,{z4\.d-z7\.d},{z8\.d-z11\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-6.d b/gas/testsuite/gas/aarch64/sme2-6.d new file mode 100644 index 00000000000..488cb099f32 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6.d @@ -0,0 +1,153 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: 25208200 cntp x0, pn0\.b, vlx2 +[^:]+: 25208200 cntp x0, pn0\.b, vlx2 +[^:]+: 2520821e cntp x30, pn0\.b, vlx2 +[^:]+: 2520821f cntp xzr, pn0\.b, vlx2 +[^:]+: 252083e0 cntp x0, pn15\.b, vlx2 +[^:]+: 25208600 cntp x0, pn0\.b, vlx4 +[^:]+: 252087ab cntp x11, pn13\.b, vlx4 +[^:]+: 25608200 cntp x0, pn0\.h, vlx2 +[^:]+: 25608200 cntp x0, pn0\.h, vlx2 +[^:]+: 2560821e cntp x30, pn0\.h, vlx2 +[^:]+: 2560821f cntp xzr, pn0\.h, vlx2 +[^:]+: 256083e0 cntp x0, pn15\.h, vlx2 +[^:]+: 25608600 cntp x0, pn0\.h, vlx4 +[^:]+: 25608334 cntp x20, pn9\.h, vlx2 +[^:]+: 25a08200 cntp x0, pn0\.s, vlx2 +[^:]+: 25a08200 cntp x0, pn0\.s, vlx2 +[^:]+: 25a0821e cntp x30, pn0\.s, vlx2 +[^:]+: 25a0821f cntp xzr, pn0\.s, vlx2 +[^:]+: 25a083e0 cntp x0, pn15\.s, vlx2 +[^:]+: 25a08600 cntp x0, pn0\.s, vlx4 +[^:]+: 25a0870f cntp x15, pn8\.s, vlx4 +[^:]+: 25e08200 cntp x0, pn0\.d, vlx2 +[^:]+: 25e08200 cntp x0, pn0\.d, vlx2 +[^:]+: 25e0821e cntp x30, pn0\.d, vlx2 +[^:]+: 25e0821f cntp xzr, pn0\.d, vlx2 +[^:]+: 25e083e0 cntp x0, pn15\.d, vlx2 +[^:]+: 25e08600 cntp x0, pn0\.d, vlx4 +[^:]+: 25e082a4 cntp x4, pn5\.d, vlx2 +[^:]+: 25207010 pext p0\.b, pn8\[0\] +[^:]+: 25207010 pext p0\.b, pn8\[0\] +[^:]+: 2520701f pext p15\.b, pn8\[0\] +[^:]+: 252070f0 pext p0\.b, pn15\[0\] +[^:]+: 25207310 pext p0\.b, pn8\[3\] +[^:]+: 25207274 pext p4\.b, pn11\[2\] +[^:]+: 25607010 pext p0\.h, pn8\[0\] +[^:]+: 25607010 pext p0\.h, pn8\[0\] +[^:]+: 2560701f pext p15\.h, pn8\[0\] +[^:]+: 256070f0 pext p0\.h, pn15\[0\] +[^:]+: 25607310 pext p0\.h, pn8\[3\] +[^:]+: 256071d5 pext p5\.h, pn14\[1\] +[^:]+: 25a07010 pext p0\.s, pn8\[0\] +[^:]+: 25a07010 pext p0\.s, pn8\[0\] +[^:]+: 25a0701f pext p15\.s, pn8\[0\] +[^:]+: 25a070f0 pext p0\.s, pn15\[0\] +[^:]+: 25a07310 pext p0\.s, pn8\[3\] +[^:]+: 25a07256 pext p6\.s, pn10\[2\] +[^:]+: 25e07010 pext p0\.d, pn8\[0\] +[^:]+: 25e07010 pext p0\.d, pn8\[0\] +[^:]+: 25e0701f pext p15\.d, pn8\[0\] +[^:]+: 25e070f0 pext p0\.d, pn15\[0\] +[^:]+: 25e07310 pext p0\.d, pn8\[3\] +[^:]+: 25e07137 pext p7\.d, pn9\[1\] +[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\] +[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\] +[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\] +[^:]+: 2520741e pext {p14\.b-p15\.b}, pn8\[0\] +[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\] +[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\] +[^:]+: 252074f0 pext {p0\.b-p1\.b}, pn15\[0\] +[^:]+: 25207510 pext {p0\.b-p1\.b}, pn8\[1\] +[^:]+: 25207497 pext {p7\.b-p8\.b}, pn12\[0\] +[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\] +[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\] +[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\] +[^:]+: 2560741e pext {p14\.h-p15\.h}, pn8\[0\] +[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\] +[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\] +[^:]+: 256074f0 pext {p0\.h-p1\.h}, pn15\[0\] +[^:]+: 25607510 pext {p0\.h-p1\.h}, pn8\[1\] +[^:]+: 256074d2 pext {p2\.h-p3\.h}, pn14\[0\] +[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\] +[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\] +[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\] +[^:]+: 25a0741e pext {p14\.s-p15\.s}, pn8\[0\] +[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\] +[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\] +[^:]+: 25a074f0 pext {p0\.s-p1\.s}, pn15\[0\] +[^:]+: 25a07510 pext {p0\.s-p1\.s}, pn8\[1\] +[^:]+: 25a074b5 pext {p5\.s-p6\.s}, pn13\[0\] +[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\] +[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\] +[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\] +[^:]+: 25e0741e pext {p14\.d-p15\.d}, pn8\[0\] +[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\] +[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\] +[^:]+: 25e074f0 pext {p0\.d-p1\.d}, pn15\[0\] +[^:]+: 25e07510 pext {p0\.d-p1\.d}, pn8\[1\] +[^:]+: 25e0743c pext {p12\.d-p13\.d}, pn9\[0\] +[^:]+: 25207810 ptrue pn8\.b +[^:]+: 25207813 ptrue pn11\.b +[^:]+: 25207817 ptrue pn15\.b +[^:]+: 25607810 ptrue pn8\.h +[^:]+: 25607811 ptrue pn9\.h +[^:]+: 25607817 ptrue pn15\.h +[^:]+: 25a07810 ptrue pn8\.s +[^:]+: 25a07816 ptrue pn14\.s +[^:]+: 25a07817 ptrue pn15\.s +[^:]+: 25e07810 ptrue pn8\.d +[^:]+: 25e07814 ptrue pn12\.d +[^:]+: 25e07817 ptrue pn15\.d +[^:]+: c1208000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^:]+: c120801e sel {z30\.b-z31\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^:]+: c1209c00 sel {z0\.b-z1\.b}, pn15, {z0\.b-z1\.b}, {z0\.b-z1\.b} +[^:]+: c12083c0 sel {z0\.b-z1\.b}, pn8, {z30\.b-z31\.b}, {z0\.b-z1\.b} +[^:]+: c13e8000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z30\.b-z31\.b} +[^:]+: c12a90c2 sel {z2\.b-z3\.b}, pn12, {z6\.b-z7\.b}, {z10\.b-z11\.b} +[^:]+: c1608000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^:]+: c160801e sel {z30\.h-z31\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^:]+: c1609c00 sel {z0\.h-z1\.h}, pn15, {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^:]+: c16083c0 sel {z0\.h-z1\.h}, pn8, {z30\.h-z31\.h}, {z0\.h-z1\.h} +[^:]+: c17e8000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z30\.h-z31\.h} +[^:]+: c17085cc sel {z12\.h-z13\.h}, pn9, {z14\.h-z15\.h}, {z16\.h-z17\.h} +[^:]+: c1a08000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a0801e sel {z30\.s-z31\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a09c00 sel {z0\.s-z1\.s}, pn15, {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a083c0 sel {z0\.s-z1\.s}, pn8, {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be8000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b88ed2 sel {z18\.s-z19\.s}, pn11, {z22\.s-z23\.s}, {z24\.s-z25\.s} +[^:]+: c1e08000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e0801e sel {z30\.d-z31\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e09c00 sel {z0\.d-z1\.d}, pn15, {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e083c0 sel {z0\.d-z1\.d}, pn8, {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe8000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1fc9b48 sel {z8\.d-z9\.d}, pn14, {z26\.d-z27\.d}, {z28\.d-z29\.d} +[^:]+: c1218000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b} +[^:]+: c121801c sel {z28\.b-z31\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b} +[^:]+: c1218380 sel {z0\.b-z3\.b}, pn8, {z28\.b-z31\.b}, {z0\.b-z3\.b} +[^:]+: c13d8000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z28\.b-z31\.b} +[^:]+: c12d8904 sel {z4\.b-z7\.b}, pn10, {z8\.b-z11\.b}, {z12\.b-z15\.b} +[^:]+: c1618000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c161801c sel {z28\.h-z31\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c1618380 sel {z0\.h-z3\.h}, pn8, {z28\.h-z31\.h}, {z0\.h-z3\.h} +[^:]+: c17d8000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z28\.h-z31\.h} +[^:]+: c1758a08 sel {z8\.h-z11\.h}, pn10, {z16\.h-z19\.h}, {z20\.h-z23\.h} +[^:]+: c1a18000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a1801c sel {z28\.s-z31\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a18380 sel {z0\.s-z3\.s}, pn8, {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd8000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b98a90 sel {z16\.s-z19\.s}, pn10, {z20\.s-z23\.s}, {z24\.s-z27\.s} +[^:]+: c1e18000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e1801c sel {z28\.d-z31\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e18380 sel {z0\.d-z3\.d}, pn8, {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd8000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1e98894 sel {z20\.d-z23\.d}, pn10, {z4\.d-z7\.d}, {z8\.d-z11\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-6.s b/gas/testsuite/gas/aarch64/sme2-6.s new file mode 100644 index 00000000000..0cc00f1387b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-6.s @@ -0,0 +1,164 @@ + cntp x0, pn0.b, vlx2 + CNTP X0, PN0.B, VLx2 + cntp x30, pn0.b, vlx2 + cntp xzr, pn0.b, vlx2 + cntp x0, pn15.b, vlx2 + cntp x0, pn0.b, vlx4 + CNTP X11, PN13.b, VLx4 + + cntp x0, pn0.h, vlx2 + CNTP X0, PN0.H, VLx2 + cntp x30, pn0.h, vlx2 + cntp xzr, pn0.h, vlx2 + cntp x0, pn15.h, vlx2 + cntp x0, pn0.h, vlx4 + CNTP X20, PN9.h, VLx2 + + cntp x0, pn0.s, vlx2 + CNTP X0, PN0.s, VLx2 + cntp x30, pn0.s, vlx2 + cntp xzr, pn0.s, vlx2 + cntp x0, pn15.s, vlx2 + cntp x0, pn0.s, vlx4 + CNTP X15, PN8.s, VLx4 + + cntp x0, pn0.d, vlx2 + CNTP X0, PN0.d, VLx2 + cntp x30, pn0.d, vlx2 + cntp xzr, pn0.d, vlx2 + cntp x0, pn15.d, vlx2 + cntp x0, pn0.d, vlx4 + CNTP X4, PN5.d, VLx2 + + pext p0.b, pn8[0] + PEXT P0.B, PN8[0] + pext p15.b, pn8[0] + pext p0.b, pn15[0] + pext p0.b, pn8[3] + pext p4.b, pn11[2] + + pext p0.h, pn8[0] + PEXT P0.H, PN8[0] + pext p15.h, pn8[0] + pext p0.h, pn15[0] + pext p0.h, pn8[3] + pext p5.h, pn14[1] + + pext p0.s, pn8[0] + PEXT P0.S, PN8[0] + pext p15.s, pn8[0] + pext p0.s, pn15[0] + pext p0.s, pn8[3] + pext p6.s, pn10[2] + + pext p0.d, pn8[0] + PEXT P0.D, PN8[0] + pext p15.d, pn8[0] + pext p0.d, pn15[0] + pext p0.d, pn8[3] + pext p7.d, pn9[1] + + pext { p0.b, p1.b }, pn8[0] + pext { p0.b - p1.b }, pn8[0] + PEXT { P0.B - P1.B }, PN8[0] + pext { p14.b - p15.b }, pn8[0] + pext { p15.b, p0.b }, pn8[0] + pext { p15.b - p0.b }, pn8[0] + pext { p0.b - p1.b }, pn15[0] + pext { p0.b - p1.b }, pn8[1] + pext { p7.b - p8.b }, pn12[0] + + pext { p0.h, p1.h }, pn8[0] + pext { p0.h - p1.h }, pn8[0] + PEXT { P0.H - P1.H }, PN8[0] + pext { p14.h - p15.h }, pn8[0] + pext { p15.h, p0.h }, pn8[0] + pext { p15.h - p0.h }, pn8[0] + pext { p0.h - p1.h }, pn15[0] + pext { p0.h - p1.h }, pn8[1] + pext { p2.h - p3.h }, pn14[0] + + pext { p0.s, p1.s }, pn8[0] + pext { p0.s - p1.s }, pn8[0] + PEXT { P0.S - P1.S }, PN8[0] + pext { p14.s - p15.s }, pn8[0] + pext { p15.s, p0.s }, pn8[0] + pext { p15.s - p0.s }, pn8[0] + pext { p0.s - p1.s }, pn15[0] + pext { p0.s - p1.s }, pn8[1] + pext { p5.s - p6.s }, pn13[0] + + pext { p0.d, p1.d }, pn8[0] + pext { p0.d - p1.d }, pn8[0] + PEXT { P0.D - P1.D }, PN8[0] + pext { p14.d - p15.d }, pn8[0] + pext { p15.d, p0.d }, pn8[0] + pext { p15.d - p0.d }, pn8[0] + pext { p0.d - p1.d }, pn15[0] + pext { p0.d - p1.d }, pn8[1] + pext { p12.d - p13.d }, pn9[0] + + ptrue pn8.b + ptrue pn11.b + ptrue pn15.b + ptrue pn8.h + ptrue pn9.h + ptrue pn15.h + ptrue pn8.s + ptrue pn14.s + ptrue pn15.s + ptrue pn8.d + ptrue pn12.d + ptrue pn15.d + + sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z30.b - z31.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn15, { z0.b - z1.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z30.b - z31.b }, { z0.b - z1.b } + sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z30.b - z31.b } + sel { z2.b - z3.b }, pn12, { z6.b - z7.b }, { z10.b - z11.b } + + sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h } + sel { z30.h - z31.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h } + sel { z0.h - z1.h }, pn15, { z0.h - z1.h }, { z0.h - z1.h } + sel { z0.h - z1.h }, pn8, { z30.h - z31.h }, { z0.h - z1.h } + sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z30.h - z31.h } + sel { z12.h - z13.h }, pn9, { z14.h - z15.h }, { z16.h - z17.h } + + sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s } + sel { z30.s - z31.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s } + sel { z0.s - z1.s }, pn15, { z0.s - z1.s }, { z0.s - z1.s } + sel { z0.s - z1.s }, pn8, { z30.s - z31.s }, { z0.s - z1.s } + sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z30.s - z31.s } + sel { z18.s - z19.s }, pn11, { z22.s - z23.s }, { z24.s - z25.s } + + sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d } + sel { z30.d - z31.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d } + sel { z0.d - z1.d }, pn15, { z0.d - z1.d }, { z0.d - z1.d } + sel { z0.d - z1.d }, pn8, { z30.d - z31.d }, { z0.d - z1.d } + sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z30.d - z31.d } + sel { z8.d - z9.d }, pn14, { z26.d - z27.d }, { z28.d - z29.d } + + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z28.b - z31.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z28.b - z31.b }, { z0.b - z3.b } + sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z28.b - z31.b } + sel { z4.b - z7.b }, pn10, { z8.b - z11.b }, { z12.b - z15.b } + + sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h } + sel { z28.h - z31.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h } + sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z0.h - z3.h } + sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z28.h - z31.h } + sel { z8.h - z11.h }, pn10, { z16.h - z19.h }, { z20.h - z23.h } + + sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s } + sel { z28.s - z31.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s } + sel { z0.s - z3.s }, pn8, { z28.s - z31.s }, { z0.s - z3.s } + sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z28.s - z31.s } + sel { z16.s - z19.s }, pn10, { z20.s - z23.s }, { z24.s - z27.s } + + sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d } + sel { z28.d - z31.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d } + sel { z0.d - z3.d }, pn8, { z28.d - z31.d }, { z0.d - z3.d } + sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z28.d - z31.d } + sel { z20.d - z23.d }, pn10, { z4.d - z7.d }, { z8.d - z11.d } diff --git a/gas/testsuite/gas/aarch64/sme2-7-invalid.d b/gas/testsuite/gas/aarch64/sme2-7-invalid.d new file mode 100644 index 00000000000..889fd417d8e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-7-invalid.s +#error_output: sme2-7-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-7-invalid.l b/gas/testsuite/gas/aarch64/sme2-7-invalid.l new file mode 100644 index 00000000000..65b4cce932a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7-invalid.l @@ -0,0 +1,20 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege 0,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,0,x0,vlx2' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,0,vlx2' +[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,0' +[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `whilege pn0\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `whilege p8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege z8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: comma expected between operands at operand 4 -- `whilege pn8\.b,x0,x0' +[^ :]+:[0-9]+: Error: operand mismatch -- `whilege pn8\.b,w0,w0,vlx2' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: whilege pn8\.b, x0, x0, vlx2 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: whilege pn8\.h, x0, x0, vlx2 +[^ :]+:[0-9]+: Info: whilege pn8\.s, x0, x0, vlx2 +[^ :]+:[0-9]+: Info: whilege pn8\.d, x0, x0, vlx2 +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,sp,x0,vlx2' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,sp,vlx2' +[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,#0' +[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,1' diff --git a/gas/testsuite/gas/aarch64/sme2-7-invalid.s b/gas/testsuite/gas/aarch64/sme2-7-invalid.s new file mode 100644 index 00000000000..0840e7f9169 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7-invalid.s @@ -0,0 +1,14 @@ + whilege 0, x0, x0, vlx2 + whilege pn8.b, 0, x0, vlx2 + whilege pn8.b, x0, 0, vlx2 + whilege pn8.b, x0, x0, 0 + + whilege pn0.b, x0, x0, vlx2 + whilege p8.b, x0, x0, vlx2 + whilege z8.b, x0, x0, vlx2 + whilege pn8.b, x0, x0 + whilege pn8.b, w0, w0, vlx2 + whilege pn8.b, sp, x0, vlx2 + whilege pn8.b, x0, sp, vlx2 + whilege pn8.b, x0, x0, #0 + whilege pn8.b, x0, x0, 1 diff --git a/gas/testsuite/gas/aarch64/sme2-7-noarch.d b/gas/testsuite/gas/aarch64/sme2-7-noarch.d new file mode 100644 index 00000000000..50ea07c98a7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-7.s +#error_output: sme2-7-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-7-noarch.l b/gas/testsuite/gas/aarch64/sme2-7-noarch.l new file mode 100644 index 00000000000..b6b3c75fda6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7-noarch.l @@ -0,0 +1,321 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn13\.d,x26,x9,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.b,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn11\.b,x20,x1,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.h,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn14\.h,x14,x25,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.s,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn9\.s,x4,x27,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx4' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.d,x0,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x30,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,xzr,x0,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x30,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,xzr,vlx2' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn13\.d,x26,x9,vlx4' diff --git a/gas/testsuite/gas/aarch64/sme2-7.d b/gas/testsuite/gas/aarch64/sme2-7.d new file mode 100644 index 00000000000..8c6fdc5d508 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7.d @@ -0,0 +1,329 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2 +[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4 +[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2 +[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4 +[^:]+: 25204017 whilege pn15\.b, x0, x0, vlx2 +[^:]+: 252043d0 whilege pn8\.b, x30, x0, vlx2 +[^:]+: 252043f0 whilege pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4010 whilege pn8\.b, x0, x30, vlx2 +[^:]+: 253f4010 whilege pn8\.b, x0, xzr, vlx2 +[^:]+: 25216293 whilege pn11\.b, x20, x1, vlx4 +[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2 +[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4 +[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2 +[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4 +[^:]+: 25604017 whilege pn15\.h, x0, x0, vlx2 +[^:]+: 256043d0 whilege pn8\.h, x30, x0, vlx2 +[^:]+: 256043f0 whilege pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4010 whilege pn8\.h, x0, x30, vlx2 +[^:]+: 257f4010 whilege pn8\.h, x0, xzr, vlx2 +[^:]+: 257961d6 whilege pn14\.h, x14, x25, vlx4 +[^:]+: 25a04010 whilege pn8\.s, x0, x0, vlx2 +[^:]+: 25a06010 whilege pn8\.s, x0, x0, vlx4 +[^:]+: 25a04010 whilege pn8\.s, x0, x0, vlx2 +[^:]+: 25a06010 whilege pn8\.s, x0, x0, vlx4 +[^:]+: 25a04017 whilege pn15\.s, x0, x0, vlx2 +[^:]+: 25a043d0 whilege pn8\.s, x30, x0, vlx2 +[^:]+: 25a043f0 whilege pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4010 whilege pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4010 whilege pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4091 whilege pn9\.s, x4, x27, vlx2 +[^:]+: 25e04010 whilege pn8\.d, x0, x0, vlx2 +[^:]+: 25e06010 whilege pn8\.d, x0, x0, vlx4 +[^:]+: 25e04010 whilege pn8\.d, x0, x0, vlx2 +[^:]+: 25e06010 whilege pn8\.d, x0, x0, vlx4 +[^:]+: 25e04017 whilege pn15\.d, x0, x0, vlx2 +[^:]+: 25e043d0 whilege pn8\.d, x30, x0, vlx2 +[^:]+: 25e043f0 whilege pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4010 whilege pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4010 whilege pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96355 whilege pn13\.d, x26, x9, vlx4 +[^:]+: 25204018 whilegt pn8\.b, x0, x0, vlx2 +[^:]+: 25206018 whilegt pn8\.b, x0, x0, vlx4 +[^:]+: 25204018 whilegt pn8\.b, x0, x0, vlx2 +[^:]+: 25206018 whilegt pn8\.b, x0, x0, vlx4 +[^:]+: 2520401f whilegt pn15\.b, x0, x0, vlx2 +[^:]+: 252043d8 whilegt pn8\.b, x30, x0, vlx2 +[^:]+: 252043f8 whilegt pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4018 whilegt pn8\.b, x0, x30, vlx2 +[^:]+: 253f4018 whilegt pn8\.b, x0, xzr, vlx2 +[^:]+: 2521629b whilegt pn11\.b, x20, x1, vlx4 +[^:]+: 25604018 whilegt pn8\.h, x0, x0, vlx2 +[^:]+: 25606018 whilegt pn8\.h, x0, x0, vlx4 +[^:]+: 25604018 whilegt pn8\.h, x0, x0, vlx2 +[^:]+: 25606018 whilegt pn8\.h, x0, x0, vlx4 +[^:]+: 2560401f whilegt pn15\.h, x0, x0, vlx2 +[^:]+: 256043d8 whilegt pn8\.h, x30, x0, vlx2 +[^:]+: 256043f8 whilegt pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4018 whilegt pn8\.h, x0, x30, vlx2 +[^:]+: 257f4018 whilegt pn8\.h, x0, xzr, vlx2 +[^:]+: 257961de whilegt pn14\.h, x14, x25, vlx4 +[^:]+: 25a04018 whilegt pn8\.s, x0, x0, vlx2 +[^:]+: 25a06018 whilegt pn8\.s, x0, x0, vlx4 +[^:]+: 25a04018 whilegt pn8\.s, x0, x0, vlx2 +[^:]+: 25a06018 whilegt pn8\.s, x0, x0, vlx4 +[^:]+: 25a0401f whilegt pn15\.s, x0, x0, vlx2 +[^:]+: 25a043d8 whilegt pn8\.s, x30, x0, vlx2 +[^:]+: 25a043f8 whilegt pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4018 whilegt pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4018 whilegt pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4099 whilegt pn9\.s, x4, x27, vlx2 +[^:]+: 25e04018 whilegt pn8\.d, x0, x0, vlx2 +[^:]+: 25e06018 whilegt pn8\.d, x0, x0, vlx4 +[^:]+: 25e04018 whilegt pn8\.d, x0, x0, vlx2 +[^:]+: 25e06018 whilegt pn8\.d, x0, x0, vlx4 +[^:]+: 25e0401f whilegt pn15\.d, x0, x0, vlx2 +[^:]+: 25e043d8 whilegt pn8\.d, x30, x0, vlx2 +[^:]+: 25e043f8 whilegt pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4018 whilegt pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4018 whilegt pn8\.d, x0, xzr, vlx2 +[^:]+: 25e9635d whilegt pn13\.d, x26, x9, vlx4 +[^:]+: 25204818 whilehi pn8\.b, x0, x0, vlx2 +[^:]+: 25206818 whilehi pn8\.b, x0, x0, vlx4 +[^:]+: 25204818 whilehi pn8\.b, x0, x0, vlx2 +[^:]+: 25206818 whilehi pn8\.b, x0, x0, vlx4 +[^:]+: 2520481f whilehi pn15\.b, x0, x0, vlx2 +[^:]+: 25204bd8 whilehi pn8\.b, x30, x0, vlx2 +[^:]+: 25204bf8 whilehi pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4818 whilehi pn8\.b, x0, x30, vlx2 +[^:]+: 253f4818 whilehi pn8\.b, x0, xzr, vlx2 +[^:]+: 25216a9b whilehi pn11\.b, x20, x1, vlx4 +[^:]+: 25604818 whilehi pn8\.h, x0, x0, vlx2 +[^:]+: 25606818 whilehi pn8\.h, x0, x0, vlx4 +[^:]+: 25604818 whilehi pn8\.h, x0, x0, vlx2 +[^:]+: 25606818 whilehi pn8\.h, x0, x0, vlx4 +[^:]+: 2560481f whilehi pn15\.h, x0, x0, vlx2 +[^:]+: 25604bd8 whilehi pn8\.h, x30, x0, vlx2 +[^:]+: 25604bf8 whilehi pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4818 whilehi pn8\.h, x0, x30, vlx2 +[^:]+: 257f4818 whilehi pn8\.h, x0, xzr, vlx2 +[^:]+: 257969de whilehi pn14\.h, x14, x25, vlx4 +[^:]+: 25a04818 whilehi pn8\.s, x0, x0, vlx2 +[^:]+: 25a06818 whilehi pn8\.s, x0, x0, vlx4 +[^:]+: 25a04818 whilehi pn8\.s, x0, x0, vlx2 +[^:]+: 25a06818 whilehi pn8\.s, x0, x0, vlx4 +[^:]+: 25a0481f whilehi pn15\.s, x0, x0, vlx2 +[^:]+: 25a04bd8 whilehi pn8\.s, x30, x0, vlx2 +[^:]+: 25a04bf8 whilehi pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4818 whilehi pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4818 whilehi pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4899 whilehi pn9\.s, x4, x27, vlx2 +[^:]+: 25e04818 whilehi pn8\.d, x0, x0, vlx2 +[^:]+: 25e06818 whilehi pn8\.d, x0, x0, vlx4 +[^:]+: 25e04818 whilehi pn8\.d, x0, x0, vlx2 +[^:]+: 25e06818 whilehi pn8\.d, x0, x0, vlx4 +[^:]+: 25e0481f whilehi pn15\.d, x0, x0, vlx2 +[^:]+: 25e04bd8 whilehi pn8\.d, x30, x0, vlx2 +[^:]+: 25e04bf8 whilehi pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4818 whilehi pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4818 whilehi pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96b5d whilehi pn13\.d, x26, x9, vlx4 +[^:]+: 25204810 whilehs pn8\.b, x0, x0, vlx2 +[^:]+: 25206810 whilehs pn8\.b, x0, x0, vlx4 +[^:]+: 25204810 whilehs pn8\.b, x0, x0, vlx2 +[^:]+: 25206810 whilehs pn8\.b, x0, x0, vlx4 +[^:]+: 25204817 whilehs pn15\.b, x0, x0, vlx2 +[^:]+: 25204bd0 whilehs pn8\.b, x30, x0, vlx2 +[^:]+: 25204bf0 whilehs pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4810 whilehs pn8\.b, x0, x30, vlx2 +[^:]+: 253f4810 whilehs pn8\.b, x0, xzr, vlx2 +[^:]+: 25216a93 whilehs pn11\.b, x20, x1, vlx4 +[^:]+: 25604810 whilehs pn8\.h, x0, x0, vlx2 +[^:]+: 25606810 whilehs pn8\.h, x0, x0, vlx4 +[^:]+: 25604810 whilehs pn8\.h, x0, x0, vlx2 +[^:]+: 25606810 whilehs pn8\.h, x0, x0, vlx4 +[^:]+: 25604817 whilehs pn15\.h, x0, x0, vlx2 +[^:]+: 25604bd0 whilehs pn8\.h, x30, x0, vlx2 +[^:]+: 25604bf0 whilehs pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4810 whilehs pn8\.h, x0, x30, vlx2 +[^:]+: 257f4810 whilehs pn8\.h, x0, xzr, vlx2 +[^:]+: 257969d6 whilehs pn14\.h, x14, x25, vlx4 +[^:]+: 25a04810 whilehs pn8\.s, x0, x0, vlx2 +[^:]+: 25a06810 whilehs pn8\.s, x0, x0, vlx4 +[^:]+: 25a04810 whilehs pn8\.s, x0, x0, vlx2 +[^:]+: 25a06810 whilehs pn8\.s, x0, x0, vlx4 +[^:]+: 25a04817 whilehs pn15\.s, x0, x0, vlx2 +[^:]+: 25a04bd0 whilehs pn8\.s, x30, x0, vlx2 +[^:]+: 25a04bf0 whilehs pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4810 whilehs pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4810 whilehs pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4891 whilehs pn9\.s, x4, x27, vlx2 +[^:]+: 25e04810 whilehs pn8\.d, x0, x0, vlx2 +[^:]+: 25e06810 whilehs pn8\.d, x0, x0, vlx4 +[^:]+: 25e04810 whilehs pn8\.d, x0, x0, vlx2 +[^:]+: 25e06810 whilehs pn8\.d, x0, x0, vlx4 +[^:]+: 25e04817 whilehs pn15\.d, x0, x0, vlx2 +[^:]+: 25e04bd0 whilehs pn8\.d, x30, x0, vlx2 +[^:]+: 25e04bf0 whilehs pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4810 whilehs pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4810 whilehs pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96b55 whilehs pn13\.d, x26, x9, vlx4 +[^:]+: 25204418 whilele pn8\.b, x0, x0, vlx2 +[^:]+: 25206418 whilele pn8\.b, x0, x0, vlx4 +[^:]+: 25204418 whilele pn8\.b, x0, x0, vlx2 +[^:]+: 25206418 whilele pn8\.b, x0, x0, vlx4 +[^:]+: 2520441f whilele pn15\.b, x0, x0, vlx2 +[^:]+: 252047d8 whilele pn8\.b, x30, x0, vlx2 +[^:]+: 252047f8 whilele pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4418 whilele pn8\.b, x0, x30, vlx2 +[^:]+: 253f4418 whilele pn8\.b, x0, xzr, vlx2 +[^:]+: 2521669b whilele pn11\.b, x20, x1, vlx4 +[^:]+: 25604418 whilele pn8\.h, x0, x0, vlx2 +[^:]+: 25606418 whilele pn8\.h, x0, x0, vlx4 +[^:]+: 25604418 whilele pn8\.h, x0, x0, vlx2 +[^:]+: 25606418 whilele pn8\.h, x0, x0, vlx4 +[^:]+: 2560441f whilele pn15\.h, x0, x0, vlx2 +[^:]+: 256047d8 whilele pn8\.h, x30, x0, vlx2 +[^:]+: 256047f8 whilele pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4418 whilele pn8\.h, x0, x30, vlx2 +[^:]+: 257f4418 whilele pn8\.h, x0, xzr, vlx2 +[^:]+: 257965de whilele pn14\.h, x14, x25, vlx4 +[^:]+: 25a04418 whilele pn8\.s, x0, x0, vlx2 +[^:]+: 25a06418 whilele pn8\.s, x0, x0, vlx4 +[^:]+: 25a04418 whilele pn8\.s, x0, x0, vlx2 +[^:]+: 25a06418 whilele pn8\.s, x0, x0, vlx4 +[^:]+: 25a0441f whilele pn15\.s, x0, x0, vlx2 +[^:]+: 25a047d8 whilele pn8\.s, x30, x0, vlx2 +[^:]+: 25a047f8 whilele pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4418 whilele pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4418 whilele pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4499 whilele pn9\.s, x4, x27, vlx2 +[^:]+: 25e04418 whilele pn8\.d, x0, x0, vlx2 +[^:]+: 25e06418 whilele pn8\.d, x0, x0, vlx4 +[^:]+: 25e04418 whilele pn8\.d, x0, x0, vlx2 +[^:]+: 25e06418 whilele pn8\.d, x0, x0, vlx4 +[^:]+: 25e0441f whilele pn15\.d, x0, x0, vlx2 +[^:]+: 25e047d8 whilele pn8\.d, x30, x0, vlx2 +[^:]+: 25e047f8 whilele pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4418 whilele pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4418 whilele pn8\.d, x0, xzr, vlx2 +[^:]+: 25e9675d whilele pn13\.d, x26, x9, vlx4 +[^:]+: 25204410 whilelt pn8\.b, x0, x0, vlx2 +[^:]+: 25206410 whilelt pn8\.b, x0, x0, vlx4 +[^:]+: 25204410 whilelt pn8\.b, x0, x0, vlx2 +[^:]+: 25206410 whilelt pn8\.b, x0, x0, vlx4 +[^:]+: 25204417 whilelt pn15\.b, x0, x0, vlx2 +[^:]+: 252047d0 whilelt pn8\.b, x30, x0, vlx2 +[^:]+: 252047f0 whilelt pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4410 whilelt pn8\.b, x0, x30, vlx2 +[^:]+: 253f4410 whilelt pn8\.b, x0, xzr, vlx2 +[^:]+: 25216693 whilelt pn11\.b, x20, x1, vlx4 +[^:]+: 25604410 whilelt pn8\.h, x0, x0, vlx2 +[^:]+: 25606410 whilelt pn8\.h, x0, x0, vlx4 +[^:]+: 25604410 whilelt pn8\.h, x0, x0, vlx2 +[^:]+: 25606410 whilelt pn8\.h, x0, x0, vlx4 +[^:]+: 25604417 whilelt pn15\.h, x0, x0, vlx2 +[^:]+: 256047d0 whilelt pn8\.h, x30, x0, vlx2 +[^:]+: 256047f0 whilelt pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4410 whilelt pn8\.h, x0, x30, vlx2 +[^:]+: 257f4410 whilelt pn8\.h, x0, xzr, vlx2 +[^:]+: 257965d6 whilelt pn14\.h, x14, x25, vlx4 +[^:]+: 25a04410 whilelt pn8\.s, x0, x0, vlx2 +[^:]+: 25a06410 whilelt pn8\.s, x0, x0, vlx4 +[^:]+: 25a04410 whilelt pn8\.s, x0, x0, vlx2 +[^:]+: 25a06410 whilelt pn8\.s, x0, x0, vlx4 +[^:]+: 25a04417 whilelt pn15\.s, x0, x0, vlx2 +[^:]+: 25a047d0 whilelt pn8\.s, x30, x0, vlx2 +[^:]+: 25a047f0 whilelt pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4410 whilelt pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4410 whilelt pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4491 whilelt pn9\.s, x4, x27, vlx2 +[^:]+: 25e04410 whilelt pn8\.d, x0, x0, vlx2 +[^:]+: 25e06410 whilelt pn8\.d, x0, x0, vlx4 +[^:]+: 25e04410 whilelt pn8\.d, x0, x0, vlx2 +[^:]+: 25e06410 whilelt pn8\.d, x0, x0, vlx4 +[^:]+: 25e04417 whilelt pn15\.d, x0, x0, vlx2 +[^:]+: 25e047d0 whilelt pn8\.d, x30, x0, vlx2 +[^:]+: 25e047f0 whilelt pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4410 whilelt pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4410 whilelt pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96755 whilelt pn13\.d, x26, x9, vlx4 +[^:]+: 25204c10 whilelo pn8\.b, x0, x0, vlx2 +[^:]+: 25206c10 whilelo pn8\.b, x0, x0, vlx4 +[^:]+: 25204c10 whilelo pn8\.b, x0, x0, vlx2 +[^:]+: 25206c10 whilelo pn8\.b, x0, x0, vlx4 +[^:]+: 25204c17 whilelo pn15\.b, x0, x0, vlx2 +[^:]+: 25204fd0 whilelo pn8\.b, x30, x0, vlx2 +[^:]+: 25204ff0 whilelo pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4c10 whilelo pn8\.b, x0, x30, vlx2 +[^:]+: 253f4c10 whilelo pn8\.b, x0, xzr, vlx2 +[^:]+: 25216e93 whilelo pn11\.b, x20, x1, vlx4 +[^:]+: 25604c10 whilelo pn8\.h, x0, x0, vlx2 +[^:]+: 25606c10 whilelo pn8\.h, x0, x0, vlx4 +[^:]+: 25604c10 whilelo pn8\.h, x0, x0, vlx2 +[^:]+: 25606c10 whilelo pn8\.h, x0, x0, vlx4 +[^:]+: 25604c17 whilelo pn15\.h, x0, x0, vlx2 +[^:]+: 25604fd0 whilelo pn8\.h, x30, x0, vlx2 +[^:]+: 25604ff0 whilelo pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4c10 whilelo pn8\.h, x0, x30, vlx2 +[^:]+: 257f4c10 whilelo pn8\.h, x0, xzr, vlx2 +[^:]+: 25796dd6 whilelo pn14\.h, x14, x25, vlx4 +[^:]+: 25a04c10 whilelo pn8\.s, x0, x0, vlx2 +[^:]+: 25a06c10 whilelo pn8\.s, x0, x0, vlx4 +[^:]+: 25a04c10 whilelo pn8\.s, x0, x0, vlx2 +[^:]+: 25a06c10 whilelo pn8\.s, x0, x0, vlx4 +[^:]+: 25a04c17 whilelo pn15\.s, x0, x0, vlx2 +[^:]+: 25a04fd0 whilelo pn8\.s, x30, x0, vlx2 +[^:]+: 25a04ff0 whilelo pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4c10 whilelo pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4c10 whilelo pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4c91 whilelo pn9\.s, x4, x27, vlx2 +[^:]+: 25e04c10 whilelo pn8\.d, x0, x0, vlx2 +[^:]+: 25e06c10 whilelo pn8\.d, x0, x0, vlx4 +[^:]+: 25e04c10 whilelo pn8\.d, x0, x0, vlx2 +[^:]+: 25e06c10 whilelo pn8\.d, x0, x0, vlx4 +[^:]+: 25e04c17 whilelo pn15\.d, x0, x0, vlx2 +[^:]+: 25e04fd0 whilelo pn8\.d, x30, x0, vlx2 +[^:]+: 25e04ff0 whilelo pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4c10 whilelo pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4c10 whilelo pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96f55 whilelo pn13\.d, x26, x9, vlx4 +[^:]+: 25204c18 whilels pn8\.b, x0, x0, vlx2 +[^:]+: 25206c18 whilels pn8\.b, x0, x0, vlx4 +[^:]+: 25204c18 whilels pn8\.b, x0, x0, vlx2 +[^:]+: 25206c18 whilels pn8\.b, x0, x0, vlx4 +[^:]+: 25204c1f whilels pn15\.b, x0, x0, vlx2 +[^:]+: 25204fd8 whilels pn8\.b, x30, x0, vlx2 +[^:]+: 25204ff8 whilels pn8\.b, xzr, x0, vlx2 +[^:]+: 253e4c18 whilels pn8\.b, x0, x30, vlx2 +[^:]+: 253f4c18 whilels pn8\.b, x0, xzr, vlx2 +[^:]+: 25216e9b whilels pn11\.b, x20, x1, vlx4 +[^:]+: 25604c18 whilels pn8\.h, x0, x0, vlx2 +[^:]+: 25606c18 whilels pn8\.h, x0, x0, vlx4 +[^:]+: 25604c18 whilels pn8\.h, x0, x0, vlx2 +[^:]+: 25606c18 whilels pn8\.h, x0, x0, vlx4 +[^:]+: 25604c1f whilels pn15\.h, x0, x0, vlx2 +[^:]+: 25604fd8 whilels pn8\.h, x30, x0, vlx2 +[^:]+: 25604ff8 whilels pn8\.h, xzr, x0, vlx2 +[^:]+: 257e4c18 whilels pn8\.h, x0, x30, vlx2 +[^:]+: 257f4c18 whilels pn8\.h, x0, xzr, vlx2 +[^:]+: 25796dde whilels pn14\.h, x14, x25, vlx4 +[^:]+: 25a04c18 whilels pn8\.s, x0, x0, vlx2 +[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4 +[^:]+: 25a04c18 whilels pn8\.s, x0, x0, vlx2 +[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4 +[^:]+: 25a04c1f whilels pn15\.s, x0, x0, vlx2 +[^:]+: 25a04fd8 whilels pn8\.s, x30, x0, vlx2 +[^:]+: 25a04ff8 whilels pn8\.s, xzr, x0, vlx2 +[^:]+: 25be4c18 whilels pn8\.s, x0, x30, vlx2 +[^:]+: 25bf4c18 whilels pn8\.s, x0, xzr, vlx2 +[^:]+: 25bb4c99 whilels pn9\.s, x4, x27, vlx2 +[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2 +[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4 +[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2 +[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4 +[^:]+: 25e04c1f whilels pn15\.d, x0, x0, vlx2 +[^:]+: 25e04fd8 whilels pn8\.d, x30, x0, vlx2 +[^:]+: 25e04ff8 whilels pn8\.d, xzr, x0, vlx2 +[^:]+: 25fe4c18 whilels pn8\.d, x0, x30, vlx2 +[^:]+: 25ff4c18 whilels pn8\.d, x0, xzr, vlx2 +[^:]+: 25e96f5d whilels pn13\.d, x26, x9, vlx4 diff --git a/gas/testsuite/gas/aarch64/sme2-7.s b/gas/testsuite/gas/aarch64/sme2-7.s new file mode 100644 index 00000000000..e064a6a6bfa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-7.s @@ -0,0 +1,351 @@ + whilege pn8.b, x0, x0, vlx2 + whilege pn8.b, x0, x0, vlx4 + WHILEGE PN8.B, X0, X0, VLx2 + WHILEGE PN8.B, X0, X0, VLx4 + whilege pn15.b, x0, x0, vlx2 + whilege pn8.b, x30, x0, vlx2 + whilege pn8.b, xzr, x0, vlx2 + whilege pn8.b, x0, x30, vlx2 + whilege pn8.b, x0, xzr, vlx2 + whilege pn11.b, x20, x1, vlx4 + + whilege pn8.h, x0, x0, vlx2 + whilege pn8.h, x0, x0, vlx4 + WHILEGE PN8.h, X0, X0, VLx2 + WHILEGE PN8.h, X0, X0, VLx4 + whilege pn15.h, x0, x0, vlx2 + whilege pn8.h, x30, x0, vlx2 + whilege pn8.h, xzr, x0, vlx2 + whilege pn8.h, x0, x30, vlx2 + whilege pn8.h, x0, xzr, vlx2 + whilege pn14.h, x14, x25, vlx4 + + whilege pn8.s, x0, x0, vlx2 + whilege pn8.s, x0, x0, vlx4 + WHILEGE PN8.s, X0, X0, VLx2 + WHILEGE PN8.s, X0, X0, VLx4 + whilege pn15.s, x0, x0, vlx2 + whilege pn8.s, x30, x0, vlx2 + whilege pn8.s, xzr, x0, vlx2 + whilege pn8.s, x0, x30, vlx2 + whilege pn8.s, x0, xzr, vlx2 + whilege pn9.s, x4, x27, vlx2 + + whilege pn8.d, x0, x0, vlx2 + whilege pn8.d, x0, x0, vlx4 + WHILEGE PN8.d, X0, X0, VLx2 + WHILEGE PN8.d, X0, X0, VLx4 + whilege pn15.d, x0, x0, vlx2 + whilege pn8.d, x30, x0, vlx2 + whilege pn8.d, xzr, x0, vlx2 + whilege pn8.d, x0, x30, vlx2 + whilege pn8.d, x0, xzr, vlx2 + whilege pn13.d, x26, x9, vlx4 + + whilegt pn8.b, x0, x0, vlx2 + whilegt pn8.b, x0, x0, vlx4 + WHILEGT PN8.B, X0, X0, VLx2 + WHILEGT PN8.B, X0, X0, VLx4 + whilegt pn15.b, x0, x0, vlx2 + whilegt pn8.b, x30, x0, vlx2 + whilegt pn8.b, xzr, x0, vlx2 + whilegt pn8.b, x0, x30, vlx2 + whilegt pn8.b, x0, xzr, vlx2 + whilegt pn11.b, x20, x1, vlx4 + + whilegt pn8.h, x0, x0, vlx2 + whilegt pn8.h, x0, x0, vlx4 + WHILEGT PN8.h, X0, X0, VLx2 + WHILEGT PN8.h, X0, X0, VLx4 + whilegt pn15.h, x0, x0, vlx2 + whilegt pn8.h, x30, x0, vlx2 + whilegt pn8.h, xzr, x0, vlx2 + whilegt pn8.h, x0, x30, vlx2 + whilegt pn8.h, x0, xzr, vlx2 + whilegt pn14.h, x14, x25, vlx4 + + whilegt pn8.s, x0, x0, vlx2 + whilegt pn8.s, x0, x0, vlx4 + WHILEGT PN8.s, X0, X0, VLx2 + WHILEGT PN8.s, X0, X0, VLx4 + whilegt pn15.s, x0, x0, vlx2 + whilegt pn8.s, x30, x0, vlx2 + whilegt pn8.s, xzr, x0, vlx2 + whilegt pn8.s, x0, x30, vlx2 + whilegt pn8.s, x0, xzr, vlx2 + whilegt pn9.s, x4, x27, vlx2 + + whilegt pn8.d, x0, x0, vlx2 + whilegt pn8.d, x0, x0, vlx4 + WHILEGT PN8.d, X0, X0, VLx2 + WHILEGT PN8.d, X0, X0, VLx4 + whilegt pn15.d, x0, x0, vlx2 + whilegt pn8.d, x30, x0, vlx2 + whilegt pn8.d, xzr, x0, vlx2 + whilegt pn8.d, x0, x30, vlx2 + whilegt pn8.d, x0, xzr, vlx2 + whilegt pn13.d, x26, x9, vlx4 + + whilehi pn8.b, x0, x0, vlx2 + whilehi pn8.b, x0, x0, vlx4 + WHILEHI PN8.B, X0, X0, VLx2 + WHILEHI PN8.B, X0, X0, VLx4 + whilehi pn15.b, x0, x0, vlx2 + whilehi pn8.b, x30, x0, vlx2 + whilehi pn8.b, xzr, x0, vlx2 + whilehi pn8.b, x0, x30, vlx2 + whilehi pn8.b, x0, xzr, vlx2 + whilehi pn11.b, x20, x1, vlx4 + + whilehi pn8.h, x0, x0, vlx2 + whilehi pn8.h, x0, x0, vlx4 + WHILEHI PN8.h, X0, X0, VLx2 + WHILEHI PN8.h, X0, X0, VLx4 + whilehi pn15.h, x0, x0, vlx2 + whilehi pn8.h, x30, x0, vlx2 + whilehi pn8.h, xzr, x0, vlx2 + whilehi pn8.h, x0, x30, vlx2 + whilehi pn8.h, x0, xzr, vlx2 + whilehi pn14.h, x14, x25, vlx4 + + whilehi pn8.s, x0, x0, vlx2 + whilehi pn8.s, x0, x0, vlx4 + WHILEHI PN8.s, X0, X0, VLx2 + WHILEHI PN8.s, X0, X0, VLx4 + whilehi pn15.s, x0, x0, vlx2 + whilehi pn8.s, x30, x0, vlx2 + whilehi pn8.s, xzr, x0, vlx2 + whilehi pn8.s, x0, x30, vlx2 + whilehi pn8.s, x0, xzr, vlx2 + whilehi pn9.s, x4, x27, vlx2 + + whilehi pn8.d, x0, x0, vlx2 + whilehi pn8.d, x0, x0, vlx4 + WHILEHI PN8.d, X0, X0, VLx2 + WHILEHI PN8.d, X0, X0, VLx4 + whilehi pn15.d, x0, x0, vlx2 + whilehi pn8.d, x30, x0, vlx2 + whilehi pn8.d, xzr, x0, vlx2 + whilehi pn8.d, x0, x30, vlx2 + whilehi pn8.d, x0, xzr, vlx2 + whilehi pn13.d, x26, x9, vlx4 + + whilehs pn8.b, x0, x0, vlx2 + whilehs pn8.b, x0, x0, vlx4 + WHILEHS PN8.B, X0, X0, VLx2 + WHILEHS PN8.B, X0, X0, VLx4 + whilehs pn15.b, x0, x0, vlx2 + whilehs pn8.b, x30, x0, vlx2 + whilehs pn8.b, xzr, x0, vlx2 + whilehs pn8.b, x0, x30, vlx2 + whilehs pn8.b, x0, xzr, vlx2 + whilehs pn11.b, x20, x1, vlx4 + + whilehs pn8.h, x0, x0, vlx2 + whilehs pn8.h, x0, x0, vlx4 + WHILEHS PN8.h, X0, X0, VLx2 + WHILEHS PN8.h, X0, X0, VLx4 + whilehs pn15.h, x0, x0, vlx2 + whilehs pn8.h, x30, x0, vlx2 + whilehs pn8.h, xzr, x0, vlx2 + whilehs pn8.h, x0, x30, vlx2 + whilehs pn8.h, x0, xzr, vlx2 + whilehs pn14.h, x14, x25, vlx4 + + whilehs pn8.s, x0, x0, vlx2 + whilehs pn8.s, x0, x0, vlx4 + WHILEHS PN8.s, X0, X0, VLx2 + WHILEHS PN8.s, X0, X0, VLx4 + whilehs pn15.s, x0, x0, vlx2 + whilehs pn8.s, x30, x0, vlx2 + whilehs pn8.s, xzr, x0, vlx2 + whilehs pn8.s, x0, x30, vlx2 + whilehs pn8.s, x0, xzr, vlx2 + whilehs pn9.s, x4, x27, vlx2 + + whilehs pn8.d, x0, x0, vlx2 + whilehs pn8.d, x0, x0, vlx4 + WHILEHS PN8.d, X0, X0, VLx2 + WHILEHS PN8.d, X0, X0, VLx4 + whilehs pn15.d, x0, x0, vlx2 + whilehs pn8.d, x30, x0, vlx2 + whilehs pn8.d, xzr, x0, vlx2 + whilehs pn8.d, x0, x30, vlx2 + whilehs pn8.d, x0, xzr, vlx2 + whilehs pn13.d, x26, x9, vlx4 + + whilele pn8.b, x0, x0, vlx2 + whilele pn8.b, x0, x0, vlx4 + WHILELE PN8.B, X0, X0, VLx2 + WHILELE PN8.B, X0, X0, VLx4 + whilele pn15.b, x0, x0, vlx2 + whilele pn8.b, x30, x0, vlx2 + whilele pn8.b, xzr, x0, vlx2 + whilele pn8.b, x0, x30, vlx2 + whilele pn8.b, x0, xzr, vlx2 + whilele pn11.b, x20, x1, vlx4 + + whilele pn8.h, x0, x0, vlx2 + whilele pn8.h, x0, x0, vlx4 + WHILELE PN8.h, X0, X0, VLx2 + WHILELE PN8.h, X0, X0, VLx4 + whilele pn15.h, x0, x0, vlx2 + whilele pn8.h, x30, x0, vlx2 + whilele pn8.h, xzr, x0, vlx2 + whilele pn8.h, x0, x30, vlx2 + whilele pn8.h, x0, xzr, vlx2 + whilele pn14.h, x14, x25, vlx4 + + whilele pn8.s, x0, x0, vlx2 + whilele pn8.s, x0, x0, vlx4 + WHILELE PN8.s, X0, X0, VLx2 + WHILELE PN8.s, X0, X0, VLx4 + whilele pn15.s, x0, x0, vlx2 + whilele pn8.s, x30, x0, vlx2 + whilele pn8.s, xzr, x0, vlx2 + whilele pn8.s, x0, x30, vlx2 + whilele pn8.s, x0, xzr, vlx2 + whilele pn9.s, x4, x27, vlx2 + + whilele pn8.d, x0, x0, vlx2 + whilele pn8.d, x0, x0, vlx4 + WHILELE PN8.d, X0, X0, VLx2 + WHILELE PN8.d, X0, X0, VLx4 + whilele pn15.d, x0, x0, vlx2 + whilele pn8.d, x30, x0, vlx2 + whilele pn8.d, xzr, x0, vlx2 + whilele pn8.d, x0, x30, vlx2 + whilele pn8.d, x0, xzr, vlx2 + whilele pn13.d, x26, x9, vlx4 + + whilelt pn8.b, x0, x0, vlx2 + whilelt pn8.b, x0, x0, vlx4 + WHILELT PN8.B, X0, X0, VLx2 + WHILELT PN8.B, X0, X0, VLx4 + whilelt pn15.b, x0, x0, vlx2 + whilelt pn8.b, x30, x0, vlx2 + whilelt pn8.b, xzr, x0, vlx2 + whilelt pn8.b, x0, x30, vlx2 + whilelt pn8.b, x0, xzr, vlx2 + whilelt pn11.b, x20, x1, vlx4 + + whilelt pn8.h, x0, x0, vlx2 + whilelt pn8.h, x0, x0, vlx4 + WHILELT PN8.h, X0, X0, VLx2 + WHILELT PN8.h, X0, X0, VLx4 + whilelt pn15.h, x0, x0, vlx2 + whilelt pn8.h, x30, x0, vlx2 + whilelt pn8.h, xzr, x0, vlx2 + whilelt pn8.h, x0, x30, vlx2 + whilelt pn8.h, x0, xzr, vlx2 + whilelt pn14.h, x14, x25, vlx4 + + whilelt pn8.s, x0, x0, vlx2 + whilelt pn8.s, x0, x0, vlx4 + WHILELT PN8.s, X0, X0, VLx2 + WHILELT PN8.s, X0, X0, VLx4 + whilelt pn15.s, x0, x0, vlx2 + whilelt pn8.s, x30, x0, vlx2 + whilelt pn8.s, xzr, x0, vlx2 + whilelt pn8.s, x0, x30, vlx2 + whilelt pn8.s, x0, xzr, vlx2 + whilelt pn9.s, x4, x27, vlx2 + + whilelt pn8.d, x0, x0, vlx2 + whilelt pn8.d, x0, x0, vlx4 + WHILELT PN8.d, X0, X0, VLx2 + WHILELT PN8.d, X0, X0, VLx4 + whilelt pn15.d, x0, x0, vlx2 + whilelt pn8.d, x30, x0, vlx2 + whilelt pn8.d, xzr, x0, vlx2 + whilelt pn8.d, x0, x30, vlx2 + whilelt pn8.d, x0, xzr, vlx2 + whilelt pn13.d, x26, x9, vlx4 + + whilelo pn8.b, x0, x0, vlx2 + whilelo pn8.b, x0, x0, vlx4 + WHILELO PN8.B, X0, X0, VLx2 + WHILELO PN8.B, X0, X0, VLx4 + whilelo pn15.b, x0, x0, vlx2 + whilelo pn8.b, x30, x0, vlx2 + whilelo pn8.b, xzr, x0, vlx2 + whilelo pn8.b, x0, x30, vlx2 + whilelo pn8.b, x0, xzr, vlx2 + whilelo pn11.b, x20, x1, vlx4 + + whilelo pn8.h, x0, x0, vlx2 + whilelo pn8.h, x0, x0, vlx4 + WHILELO PN8.h, X0, X0, VLx2 + WHILELO PN8.h, X0, X0, VLx4 + whilelo pn15.h, x0, x0, vlx2 + whilelo pn8.h, x30, x0, vlx2 + whilelo pn8.h, xzr, x0, vlx2 + whilelo pn8.h, x0, x30, vlx2 + whilelo pn8.h, x0, xzr, vlx2 + whilelo pn14.h, x14, x25, vlx4 + + whilelo pn8.s, x0, x0, vlx2 + whilelo pn8.s, x0, x0, vlx4 + WHILELO PN8.s, X0, X0, VLx2 + WHILELO PN8.s, X0, X0, VLx4 + whilelo pn15.s, x0, x0, vlx2 + whilelo pn8.s, x30, x0, vlx2 + whilelo pn8.s, xzr, x0, vlx2 + whilelo pn8.s, x0, x30, vlx2 + whilelo pn8.s, x0, xzr, vlx2 + whilelo pn9.s, x4, x27, vlx2 + + whilelo pn8.d, x0, x0, vlx2 + whilelo pn8.d, x0, x0, vlx4 + WHILELO PN8.d, X0, X0, VLx2 + WHILELO PN8.d, X0, X0, VLx4 + whilelo pn15.d, x0, x0, vlx2 + whilelo pn8.d, x30, x0, vlx2 + whilelo pn8.d, xzr, x0, vlx2 + whilelo pn8.d, x0, x30, vlx2 + whilelo pn8.d, x0, xzr, vlx2 + whilelo pn13.d, x26, x9, vlx4 + + whilels pn8.b, x0, x0, vlx2 + whilels pn8.b, x0, x0, vlx4 + WHILELS PN8.B, X0, X0, VLx2 + WHILELS PN8.B, X0, X0, VLx4 + whilels pn15.b, x0, x0, vlx2 + whilels pn8.b, x30, x0, vlx2 + whilels pn8.b, xzr, x0, vlx2 + whilels pn8.b, x0, x30, vlx2 + whilels pn8.b, x0, xzr, vlx2 + whilels pn11.b, x20, x1, vlx4 + + whilels pn8.h, x0, x0, vlx2 + whilels pn8.h, x0, x0, vlx4 + WHILELS PN8.h, X0, X0, VLx2 + WHILELS PN8.h, X0, X0, VLx4 + whilels pn15.h, x0, x0, vlx2 + whilels pn8.h, x30, x0, vlx2 + whilels pn8.h, xzr, x0, vlx2 + whilels pn8.h, x0, x30, vlx2 + whilels pn8.h, x0, xzr, vlx2 + whilels pn14.h, x14, x25, vlx4 + + whilels pn8.s, x0, x0, vlx2 + whilels pn8.s, x0, x0, vlx4 + WHILELS PN8.s, X0, X0, VLx2 + WHILELS PN8.s, X0, X0, VLx4 + whilels pn15.s, x0, x0, vlx2 + whilels pn8.s, x30, x0, vlx2 + whilels pn8.s, xzr, x0, vlx2 + whilels pn8.s, x0, x30, vlx2 + whilels pn8.s, x0, xzr, vlx2 + whilels pn9.s, x4, x27, vlx2 + + whilels pn8.d, x0, x0, vlx2 + whilels pn8.d, x0, x0, vlx4 + WHILELS PN8.d, X0, X0, VLx2 + WHILELS PN8.d, X0, X0, VLx4 + whilels pn15.d, x0, x0, vlx2 + whilels pn8.d, x30, x0, vlx2 + whilels pn8.d, xzr, x0, vlx2 + whilels pn8.d, x0, x30, vlx2 + whilels pn8.d, x0, xzr, vlx2 + whilels pn13.d, x26, x9, vlx4 diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l index 70cfd59b4c1..99aa2860b23 100644 --- a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l +++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l @@ -1,4 +1,7 @@ [^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel 0,pn0,p0\.b\[w12,0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `psel pn0,0,p0\.b\[w12,0\]' +[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `psel pn0,pn0,0' [^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `psel pn0,p0,p0\.b\[w12,0\]' [^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel pn,pn0,p0\.b\[w12,0\]' [^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel p0,p0,pn0\.b\[w12,0\]' diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s index c0da1d78587..c131457464a 100644 --- a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s +++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s @@ -1,3 +1,7 @@ + psel 0, pn0, p0.b[w12, 0] + psel pn0, 0, p0.b[w12, 0] + psel pn0, pn0, 0 + psel pn0, p0, p0.b[w12, 0] psel pn, pn0, p0.b[w12, 0] psel p0, p0, pn0.b[w12, 0] diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d new file mode 100644 index 00000000000..79d4b38d6bb --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sve2-sme2-2-invalid.s +#error_output: sve2-sme2-2-invalid.l diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l new file mode 100644 index 00000000000..161ea7a0c5b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l @@ -0,0 +1,25 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b},x0,x0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p1\.b-p2\.b},x0,x0' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p2\.b},x0,x0' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p3\.b},x0,x0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p15\.b-p0\.b},x0,x0' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 1 -- `whilege {p0\.b,p8\.b},x0,x0' +[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `whilege {pn0\.b-pn1\.b},x0,x0' +[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `whilege {p0-p1},x0,x0' +[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.q-p1\.q},x0,x0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0 +[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0 +[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0 +[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.b-p1\.b},w0,w0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0 +[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0 +[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0 +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege {p0\.b-p1\.b},sp,x0' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege {p0\.b-p1\.b},x0,sp' diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s new file mode 100644 index 00000000000..7f23473c7cc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s @@ -0,0 +1,12 @@ + whilege { p0.b }, x0, x0 + whilege { p1.b - p2.b }, x0, x0 + whilege { p0.b - p2.b }, x0, x0 + whilege { p0.b - p3.b }, x0, x0 + whilege { p15.b - p0.b }, x0, x0 + whilege { p0.b, p8.b }, x0, x0 + whilege { pn0.b - pn1.b }, x0, x0 + whilege { p0 - p1 }, x0, x0 + whilege { p0.q - p1.q }, x0, x0 + whilege { p0.b - p1.b }, w0, w0 + whilege { p0.b - p1.b }, sp, x0 + whilege { p0.b - p1.b }, x0, sp diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d b/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d new file mode 100644 index 00000000000..bbb1787bdaa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sve2-sme2-2.s +#error_output: sve2-sme2-2-noarch.l diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l b/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l new file mode 100644 index 00000000000..3152dd8a809 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l @@ -0,0 +1,257 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.d-p5\.d},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.B-P1\.B},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.b-p15\.b},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.b-p5\.b},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.h-P1\.h},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.h-p15\.h},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.h-p5\.h},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.s-P1\.s},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.s-p15\.s},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.s-p5\.s},x17,x19' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.d-P1\.d},X0,X0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.d-p15\.d},x0,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x30,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},xzr,x0' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x30' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.d-p5\.d},x17,x19' diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2.d b/gas/testsuite/gas/aarch64/sve2-sme2-2.d new file mode 100644 index 00000000000..9e60d1fd9b0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2.d @@ -0,0 +1,265 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: 25205010 whilege {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205010 whilege {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520501e whilege {p14\.b-p15\.b}, x0, x0 +[^:]+: 252053d0 whilege {p0\.b-p1\.b}, x30, x0 +[^:]+: 252053f0 whilege {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5010 whilege {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5010 whilege {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335234 whilege {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605010 whilege {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605010 whilege {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560501e whilege {p14\.h-p15\.h}, x0, x0 +[^:]+: 256053d0 whilege {p0\.h-p1\.h}, x30, x0 +[^:]+: 256053f0 whilege {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5010 whilege {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5010 whilege {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735234 whilege {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05010 whilege {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05010 whilege {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0501e whilege {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a053d0 whilege {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a053f0 whilege {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5010 whilege {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5010 whilege {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35234 whilege {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05010 whilege {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05010 whilege {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0501e whilege {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e053d0 whilege {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e053f0 whilege {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5010 whilege {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5010 whilege {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35234 whilege {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205011 whilegt {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205011 whilegt {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520501f whilegt {p14\.b-p15\.b}, x0, x0 +[^:]+: 252053d1 whilegt {p0\.b-p1\.b}, x30, x0 +[^:]+: 252053f1 whilegt {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5011 whilegt {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5011 whilegt {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335235 whilegt {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605011 whilegt {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605011 whilegt {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560501f whilegt {p14\.h-p15\.h}, x0, x0 +[^:]+: 256053d1 whilegt {p0\.h-p1\.h}, x30, x0 +[^:]+: 256053f1 whilegt {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5011 whilegt {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5011 whilegt {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735235 whilegt {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05011 whilegt {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05011 whilegt {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0501f whilegt {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a053d1 whilegt {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a053f1 whilegt {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5011 whilegt {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5011 whilegt {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35235 whilegt {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05011 whilegt {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05011 whilegt {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0501f whilegt {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e053d1 whilegt {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e053f1 whilegt {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5011 whilegt {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5011 whilegt {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35235 whilegt {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205811 whilehi {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205811 whilehi {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520581f whilehi {p14\.b-p15\.b}, x0, x0 +[^:]+: 25205bd1 whilehi {p0\.b-p1\.b}, x30, x0 +[^:]+: 25205bf1 whilehi {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5811 whilehi {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5811 whilehi {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335a35 whilehi {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605811 whilehi {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605811 whilehi {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560581f whilehi {p14\.h-p15\.h}, x0, x0 +[^:]+: 25605bd1 whilehi {p0\.h-p1\.h}, x30, x0 +[^:]+: 25605bf1 whilehi {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5811 whilehi {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5811 whilehi {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735a35 whilehi {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05811 whilehi {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05811 whilehi {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0581f whilehi {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a05bd1 whilehi {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a05bf1 whilehi {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5811 whilehi {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5811 whilehi {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35a35 whilehi {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05811 whilehi {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05811 whilehi {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0581f whilehi {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e05bd1 whilehi {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e05bf1 whilehi {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5811 whilehi {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5811 whilehi {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35a35 whilehi {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205810 whilehs {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205810 whilehs {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520581e whilehs {p14\.b-p15\.b}, x0, x0 +[^:]+: 25205bd0 whilehs {p0\.b-p1\.b}, x30, x0 +[^:]+: 25205bf0 whilehs {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5810 whilehs {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5810 whilehs {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335a34 whilehs {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605810 whilehs {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605810 whilehs {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560581e whilehs {p14\.h-p15\.h}, x0, x0 +[^:]+: 25605bd0 whilehs {p0\.h-p1\.h}, x30, x0 +[^:]+: 25605bf0 whilehs {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5810 whilehs {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5810 whilehs {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735a34 whilehs {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05810 whilehs {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05810 whilehs {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0581e whilehs {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a05bd0 whilehs {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a05bf0 whilehs {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5810 whilehs {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5810 whilehs {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35a34 whilehs {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05810 whilehs {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05810 whilehs {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0581e whilehs {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e05bd0 whilehs {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e05bf0 whilehs {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5810 whilehs {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5810 whilehs {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35a34 whilehs {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205411 whilele {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205411 whilele {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520541f whilele {p14\.b-p15\.b}, x0, x0 +[^:]+: 252057d1 whilele {p0\.b-p1\.b}, x30, x0 +[^:]+: 252057f1 whilele {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5411 whilele {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5411 whilele {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335635 whilele {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605411 whilele {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605411 whilele {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560541f whilele {p14\.h-p15\.h}, x0, x0 +[^:]+: 256057d1 whilele {p0\.h-p1\.h}, x30, x0 +[^:]+: 256057f1 whilele {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5411 whilele {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5411 whilele {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735635 whilele {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05411 whilele {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05411 whilele {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0541f whilele {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a057d1 whilele {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a057f1 whilele {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5411 whilele {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5411 whilele {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35635 whilele {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05411 whilele {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05411 whilele {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0541f whilele {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e057d1 whilele {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e057f1 whilele {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5411 whilele {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5411 whilele {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35635 whilele {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205c10 whilelo {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205c10 whilelo {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205c1e whilelo {p14\.b-p15\.b}, x0, x0 +[^:]+: 25205fd0 whilelo {p0\.b-p1\.b}, x30, x0 +[^:]+: 25205ff0 whilelo {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5c10 whilelo {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5c10 whilelo {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335e34 whilelo {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605c10 whilelo {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605c10 whilelo {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605c1e whilelo {p14\.h-p15\.h}, x0, x0 +[^:]+: 25605fd0 whilelo {p0\.h-p1\.h}, x30, x0 +[^:]+: 25605ff0 whilelo {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5c10 whilelo {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5c10 whilelo {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735e34 whilelo {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05c10 whilelo {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05c10 whilelo {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05c1e whilelo {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a05fd0 whilelo {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a05ff0 whilelo {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5c10 whilelo {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5c10 whilelo {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35e34 whilelo {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05c10 whilelo {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05c10 whilelo {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05c1e whilelo {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e05fd0 whilelo {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e05ff0 whilelo {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5c10 whilelo {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5c10 whilelo {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35e34 whilelo {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205c1f whilels {p14\.b-p15\.b}, x0, x0 +[^:]+: 25205fd1 whilels {p0\.b-p1\.b}, x30, x0 +[^:]+: 25205ff1 whilels {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5c11 whilels {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5c11 whilels {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335e35 whilels {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605c1f whilels {p14\.h-p15\.h}, x0, x0 +[^:]+: 25605fd1 whilels {p0\.h-p1\.h}, x30, x0 +[^:]+: 25605ff1 whilels {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5c11 whilels {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5c11 whilels {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735e35 whilels {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05c1f whilels {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a05fd1 whilels {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a05ff1 whilels {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5c11 whilels {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5c11 whilels {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35e35 whilels {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05c1f whilels {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e05fd1 whilels {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e05ff1 whilels {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5c11 whilels {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5c11 whilels {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35e35 whilels {p4\.d-p5\.d}, x17, x19 +[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0 +[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0 +[^:]+: 2520541e whilelt {p14\.b-p15\.b}, x0, x0 +[^:]+: 252057d0 whilelt {p0\.b-p1\.b}, x30, x0 +[^:]+: 252057f0 whilelt {p0\.b-p1\.b}, xzr, x0 +[^:]+: 253e5410 whilelt {p0\.b-p1\.b}, x0, x30 +[^:]+: 253f5410 whilelt {p0\.b-p1\.b}, x0, xzr +[^:]+: 25335634 whilelt {p4\.b-p5\.b}, x17, x19 +[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0 +[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0 +[^:]+: 2560541e whilelt {p14\.h-p15\.h}, x0, x0 +[^:]+: 256057d0 whilelt {p0\.h-p1\.h}, x30, x0 +[^:]+: 256057f0 whilelt {p0\.h-p1\.h}, xzr, x0 +[^:]+: 257e5410 whilelt {p0\.h-p1\.h}, x0, x30 +[^:]+: 257f5410 whilelt {p0\.h-p1\.h}, x0, xzr +[^:]+: 25735634 whilelt {p4\.h-p5\.h}, x17, x19 +[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0 +[^:]+: 25a0541e whilelt {p14\.s-p15\.s}, x0, x0 +[^:]+: 25a057d0 whilelt {p0\.s-p1\.s}, x30, x0 +[^:]+: 25a057f0 whilelt {p0\.s-p1\.s}, xzr, x0 +[^:]+: 25be5410 whilelt {p0\.s-p1\.s}, x0, x30 +[^:]+: 25bf5410 whilelt {p0\.s-p1\.s}, x0, xzr +[^:]+: 25b35634 whilelt {p4\.s-p5\.s}, x17, x19 +[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0 +[^:]+: 25e0541e whilelt {p14\.d-p15\.d}, x0, x0 +[^:]+: 25e057d0 whilelt {p0\.d-p1\.d}, x30, x0 +[^:]+: 25e057f0 whilelt {p0\.d-p1\.d}, xzr, x0 +[^:]+: 25fe5410 whilelt {p0\.d-p1\.d}, x0, x30 +[^:]+: 25ff5410 whilelt {p0\.d-p1\.d}, x0, xzr +[^:]+: 25f35634 whilelt {p4\.d-p5\.d}, x17, x19 diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2.s b/gas/testsuite/gas/aarch64/sve2-sme2-2.s new file mode 100644 index 00000000000..b9175e80d7d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-sme2-2.s @@ -0,0 +1,287 @@ + whilege { p0.b - p1.b }, x0, x0 + WHILEGE { P0.B - P1.B }, X0, X0 + whilege { p14.b - p15.b }, x0, x0 + whilege { p0.b - p1.b }, x30, x0 + whilege { p0.b - p1.b }, xzr, x0 + whilege { p0.b - p1.b }, x0, x30 + whilege { p0.b - p1.b }, x0, xzr + whilege { p4.b - p5.b }, x17, x19 + + whilege { p0.h - p1.h }, x0, x0 + WHILEGE { P0.h - P1.h }, X0, X0 + whilege { p14.h - p15.h }, x0, x0 + whilege { p0.h - p1.h }, x30, x0 + whilege { p0.h - p1.h }, xzr, x0 + whilege { p0.h - p1.h }, x0, x30 + whilege { p0.h - p1.h }, x0, xzr + whilege { p4.h - p5.h }, x17, x19 + + whilege { p0.s - p1.s }, x0, x0 + WHILEGE { P0.s - P1.s }, X0, X0 + whilege { p14.s - p15.s }, x0, x0 + whilege { p0.s - p1.s }, x30, x0 + whilege { p0.s - p1.s }, xzr, x0 + whilege { p0.s - p1.s }, x0, x30 + whilege { p0.s - p1.s }, x0, xzr + whilege { p4.s - p5.s }, x17, x19 + + whilege { p0.d - p1.d }, x0, x0 + WHILEGE { P0.d - P1.d }, X0, X0 + whilege { p14.d - p15.d }, x0, x0 + whilege { p0.d - p1.d }, x30, x0 + whilege { p0.d - p1.d }, xzr, x0 + whilege { p0.d - p1.d }, x0, x30 + whilege { p0.d - p1.d }, x0, xzr + whilege { p4.d - p5.d }, x17, x19 + + whilegt { p0.b - p1.b }, x0, x0 + WHILEGT { P0.B - P1.B }, X0, X0 + whilegt { p14.b - p15.b }, x0, x0 + whilegt { p0.b - p1.b }, x30, x0 + whilegt { p0.b - p1.b }, xzr, x0 + whilegt { p0.b - p1.b }, x0, x30 + whilegt { p0.b - p1.b }, x0, xzr + whilegt { p4.b - p5.b }, x17, x19 + + whilegt { p0.h - p1.h }, x0, x0 + WHILEGT { P0.h - P1.h }, X0, X0 + whilegt { p14.h - p15.h }, x0, x0 + whilegt { p0.h - p1.h }, x30, x0 + whilegt { p0.h - p1.h }, xzr, x0 + whilegt { p0.h - p1.h }, x0, x30 + whilegt { p0.h - p1.h }, x0, xzr + whilegt { p4.h - p5.h }, x17, x19 + + whilegt { p0.s - p1.s }, x0, x0 + WHILEGT { P0.s - P1.s }, X0, X0 + whilegt { p14.s - p15.s }, x0, x0 + whilegt { p0.s - p1.s }, x30, x0 + whilegt { p0.s - p1.s }, xzr, x0 + whilegt { p0.s - p1.s }, x0, x30 + whilegt { p0.s - p1.s }, x0, xzr + whilegt { p4.s - p5.s }, x17, x19 + + whilegt { p0.d - p1.d }, x0, x0 + WHILEGT { P0.d - P1.d }, X0, X0 + whilegt { p14.d - p15.d }, x0, x0 + whilegt { p0.d - p1.d }, x30, x0 + whilegt { p0.d - p1.d }, xzr, x0 + whilegt { p0.d - p1.d }, x0, x30 + whilegt { p0.d - p1.d }, x0, xzr + whilegt { p4.d - p5.d }, x17, x19 + + whilehi { p0.b - p1.b }, x0, x0 + WHILEHI { P0.B - P1.B }, X0, X0 + whilehi { p14.b - p15.b }, x0, x0 + whilehi { p0.b - p1.b }, x30, x0 + whilehi { p0.b - p1.b }, xzr, x0 + whilehi { p0.b - p1.b }, x0, x30 + whilehi { p0.b - p1.b }, x0, xzr + whilehi { p4.b - p5.b }, x17, x19 + + whilehi { p0.h - p1.h }, x0, x0 + WHILEHI { P0.h - P1.h }, X0, X0 + whilehi { p14.h - p15.h }, x0, x0 + whilehi { p0.h - p1.h }, x30, x0 + whilehi { p0.h - p1.h }, xzr, x0 + whilehi { p0.h - p1.h }, x0, x30 + whilehi { p0.h - p1.h }, x0, xzr + whilehi { p4.h - p5.h }, x17, x19 + + whilehi { p0.s - p1.s }, x0, x0 + WHILEHI { P0.s - P1.s }, X0, X0 + whilehi { p14.s - p15.s }, x0, x0 + whilehi { p0.s - p1.s }, x30, x0 + whilehi { p0.s - p1.s }, xzr, x0 + whilehi { p0.s - p1.s }, x0, x30 + whilehi { p0.s - p1.s }, x0, xzr + whilehi { p4.s - p5.s }, x17, x19 + + whilehi { p0.d - p1.d }, x0, x0 + WHILEHI { P0.d - P1.d }, X0, X0 + whilehi { p14.d - p15.d }, x0, x0 + whilehi { p0.d - p1.d }, x30, x0 + whilehi { p0.d - p1.d }, xzr, x0 + whilehi { p0.d - p1.d }, x0, x30 + whilehi { p0.d - p1.d }, x0, xzr + whilehi { p4.d - p5.d }, x17, x19 + + whilehs { p0.b - p1.b }, x0, x0 + WHILEHS { P0.B - P1.B }, X0, X0 + whilehs { p14.b - p15.b }, x0, x0 + whilehs { p0.b - p1.b }, x30, x0 + whilehs { p0.b - p1.b }, xzr, x0 + whilehs { p0.b - p1.b }, x0, x30 + whilehs { p0.b - p1.b }, x0, xzr + whilehs { p4.b - p5.b }, x17, x19 + + whilehs { p0.h - p1.h }, x0, x0 + WHILEHS { P0.h - P1.h }, X0, X0 + whilehs { p14.h - p15.h }, x0, x0 + whilehs { p0.h - p1.h }, x30, x0 + whilehs { p0.h - p1.h }, xzr, x0 + whilehs { p0.h - p1.h }, x0, x30 + whilehs { p0.h - p1.h }, x0, xzr + whilehs { p4.h - p5.h }, x17, x19 + + whilehs { p0.s - p1.s }, x0, x0 + WHILEHS { P0.s - P1.s }, X0, X0 + whilehs { p14.s - p15.s }, x0, x0 + whilehs { p0.s - p1.s }, x30, x0 + whilehs { p0.s - p1.s }, xzr, x0 + whilehs { p0.s - p1.s }, x0, x30 + whilehs { p0.s - p1.s }, x0, xzr + whilehs { p4.s - p5.s }, x17, x19 + + whilehs { p0.d - p1.d }, x0, x0 + WHILEHS { P0.d - P1.d }, X0, X0 + whilehs { p14.d - p15.d }, x0, x0 + whilehs { p0.d - p1.d }, x30, x0 + whilehs { p0.d - p1.d }, xzr, x0 + whilehs { p0.d - p1.d }, x0, x30 + whilehs { p0.d - p1.d }, x0, xzr + whilehs { p4.d - p5.d }, x17, x19 + + whilele { p0.b - p1.b }, x0, x0 + WHILELE { P0.B - P1.B }, X0, X0 + whilele { p14.b - p15.b }, x0, x0 + whilele { p0.b - p1.b }, x30, x0 + whilele { p0.b - p1.b }, xzr, x0 + whilele { p0.b - p1.b }, x0, x30 + whilele { p0.b - p1.b }, x0, xzr + whilele { p4.b - p5.b }, x17, x19 + + whilele { p0.h - p1.h }, x0, x0 + WHILELE { P0.h - P1.h }, X0, X0 + whilele { p14.h - p15.h }, x0, x0 + whilele { p0.h - p1.h }, x30, x0 + whilele { p0.h - p1.h }, xzr, x0 + whilele { p0.h - p1.h }, x0, x30 + whilele { p0.h - p1.h }, x0, xzr + whilele { p4.h - p5.h }, x17, x19 + + whilele { p0.s - p1.s }, x0, x0 + WHILELE { P0.s - P1.s }, X0, X0 + whilele { p14.s - p15.s }, x0, x0 + whilele { p0.s - p1.s }, x30, x0 + whilele { p0.s - p1.s }, xzr, x0 + whilele { p0.s - p1.s }, x0, x30 + whilele { p0.s - p1.s }, x0, xzr + whilele { p4.s - p5.s }, x17, x19 + + whilele { p0.d - p1.d }, x0, x0 + WHILELE { P0.d - P1.d }, X0, X0 + whilele { p14.d - p15.d }, x0, x0 + whilele { p0.d - p1.d }, x30, x0 + whilele { p0.d - p1.d }, xzr, x0 + whilele { p0.d - p1.d }, x0, x30 + whilele { p0.d - p1.d }, x0, xzr + whilele { p4.d - p5.d }, x17, x19 + + whilelo { p0.b - p1.b }, x0, x0 + WHILELO { P0.B - P1.B }, X0, X0 + whilelo { p14.b - p15.b }, x0, x0 + whilelo { p0.b - p1.b }, x30, x0 + whilelo { p0.b - p1.b }, xzr, x0 + whilelo { p0.b - p1.b }, x0, x30 + whilelo { p0.b - p1.b }, x0, xzr + whilelo { p4.b - p5.b }, x17, x19 + + whilelo { p0.h - p1.h }, x0, x0 + WHILELO { P0.h - P1.h }, X0, X0 + whilelo { p14.h - p15.h }, x0, x0 + whilelo { p0.h - p1.h }, x30, x0 + whilelo { p0.h - p1.h }, xzr, x0 + whilelo { p0.h - p1.h }, x0, x30 + whilelo { p0.h - p1.h }, x0, xzr + whilelo { p4.h - p5.h }, x17, x19 + + whilelo { p0.s - p1.s }, x0, x0 + WHILELO { P0.s - P1.s }, X0, X0 + whilelo { p14.s - p15.s }, x0, x0 + whilelo { p0.s - p1.s }, x30, x0 + whilelo { p0.s - p1.s }, xzr, x0 + whilelo { p0.s - p1.s }, x0, x30 + whilelo { p0.s - p1.s }, x0, xzr + whilelo { p4.s - p5.s }, x17, x19 + + whilelo { p0.d - p1.d }, x0, x0 + WHILELO { P0.d - P1.d }, X0, X0 + whilelo { p14.d - p15.d }, x0, x0 + whilelo { p0.d - p1.d }, x30, x0 + whilelo { p0.d - p1.d }, xzr, x0 + whilelo { p0.d - p1.d }, x0, x30 + whilelo { p0.d - p1.d }, x0, xzr + whilelo { p4.d - p5.d }, x17, x19 + + whilels { p0.b - p1.b }, x0, x0 + WHILELS { P0.B - P1.B }, X0, X0 + whilels { p14.b - p15.b }, x0, x0 + whilels { p0.b - p1.b }, x30, x0 + whilels { p0.b - p1.b }, xzr, x0 + whilels { p0.b - p1.b }, x0, x30 + whilels { p0.b - p1.b }, x0, xzr + whilels { p4.b - p5.b }, x17, x19 + + whilels { p0.h - p1.h }, x0, x0 + WHILELS { P0.h - P1.h }, X0, X0 + whilels { p14.h - p15.h }, x0, x0 + whilels { p0.h - p1.h }, x30, x0 + whilels { p0.h - p1.h }, xzr, x0 + whilels { p0.h - p1.h }, x0, x30 + whilels { p0.h - p1.h }, x0, xzr + whilels { p4.h - p5.h }, x17, x19 + + whilels { p0.s - p1.s }, x0, x0 + WHILELS { P0.s - P1.s }, X0, X0 + whilels { p14.s - p15.s }, x0, x0 + whilels { p0.s - p1.s }, x30, x0 + whilels { p0.s - p1.s }, xzr, x0 + whilels { p0.s - p1.s }, x0, x30 + whilels { p0.s - p1.s }, x0, xzr + whilels { p4.s - p5.s }, x17, x19 + + whilels { p0.d - p1.d }, x0, x0 + WHILELS { P0.d - P1.d }, X0, X0 + whilels { p14.d - p15.d }, x0, x0 + whilels { p0.d - p1.d }, x30, x0 + whilels { p0.d - p1.d }, xzr, x0 + whilels { p0.d - p1.d }, x0, x30 + whilels { p0.d - p1.d }, x0, xzr + whilels { p4.d - p5.d }, x17, x19 + + whilelt { p0.b - p1.b }, x0, x0 + WHILELT { P0.B - P1.B }, X0, X0 + whilelt { p14.b - p15.b }, x0, x0 + whilelt { p0.b - p1.b }, x30, x0 + whilelt { p0.b - p1.b }, xzr, x0 + whilelt { p0.b - p1.b }, x0, x30 + whilelt { p0.b - p1.b }, x0, xzr + whilelt { p4.b - p5.b }, x17, x19 + + whilelt { p0.h - p1.h }, x0, x0 + WHILELT { P0.h - P1.h }, X0, X0 + whilelt { p14.h - p15.h }, x0, x0 + whilelt { p0.h - p1.h }, x30, x0 + whilelt { p0.h - p1.h }, xzr, x0 + whilelt { p0.h - p1.h }, x0, x30 + whilelt { p0.h - p1.h }, x0, xzr + whilelt { p4.h - p5.h }, x17, x19 + + whilelt { p0.s - p1.s }, x0, x0 + WHILELT { P0.s - P1.s }, X0, X0 + whilelt { p14.s - p15.s }, x0, x0 + whilelt { p0.s - p1.s }, x30, x0 + whilelt { p0.s - p1.s }, xzr, x0 + whilelt { p0.s - p1.s }, x0, x30 + whilelt { p0.s - p1.s }, x0, xzr + whilelt { p4.s - p5.s }, x17, x19 + + whilelt { p0.d - p1.d }, x0, x0 + WHILELT { P0.d - P1.d }, X0, X0 + whilelt { p14.d - p15.d }, x0, x0 + whilelt { p0.d - p1.d }, x30, x0 + whilelt { p0.d - p1.d }, xzr, x0 + whilelt { p0.d - p1.d }, x0, x30 + whilelt { p0.d - p1.d }, x0, xzr + whilelt { p4.d - p5.d }, x17, x19 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d34cea5efca..ee0a3b65ab0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -487,6 +487,8 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ + AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ @@ -497,8 +499,14 @@ enum aarch64_opnd AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */ AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ + AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */ + AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */ AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */ + AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */ + AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */ + AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[{, #}]. */ @@ -507,6 +515,8 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ + AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ @@ -1559,6 +1569,7 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); extern const char *const aarch64_sve_pattern_array[32]; extern const char *const aarch64_sve_prfop_array[16]; +extern const char *const aarch64_sme_vlxn_array[2]; #ifdef __cplusplus } diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 6775d2264ea..9302253db59 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -667,10 +667,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 220: - case 221: - case 226: - case 227: + case 222: + case 223: + case 230: + case 231: + case 232: + case 233: return aarch64_ins_regno (self, info, code, inst, errors); case 15: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -682,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 237: + case 247: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -727,10 +729,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 228: case 236: - case 241: - case 242: + case 244: + case 245: + case 246: + case 251: + case 252: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -889,35 +893,42 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sve_index (self, info, code, inst, errors); case 211: case 213: + case 229: return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 214: case 215: case 216: case 217: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 218: case 219: + case 228: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 220: + case 221: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 222: case 224: - case 229: + case 226: + case 237: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 223: case 225: + case 227: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 230: - case 231: - case 232: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); - case 233: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 234: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 235: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_simple_index (self, info, code, inst, errors); case 238: case 239: case 240: + return aarch64_ins_sme_za_array (self, info, code, inst, errors); + case 241: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 242: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 243: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 248: + case 249: + case 250: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 42cc6f75677..acfec3773dc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -57,17 +57,17 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) va_end (va); } -/* Insert a raw field value VALUE into all fields in SELF->fields. +/* Insert a raw field value VALUE into all fields in SELF->fields after START. The least significant bit goes in the final field. */ static void -insert_all_fields (const aarch64_operand *self, aarch64_insn *code, - aarch64_insn value) +insert_all_fields_after (const aarch64_operand *self, unsigned int start, + aarch64_insn *code, aarch64_insn value) { unsigned int i; enum aarch64_field_kind kind; - for (i = ARRAY_SIZE (self->fields); i-- > 0; ) + for (i = ARRAY_SIZE (self->fields); i-- > start; ) if (self->fields[i] != FLD_NIL) { kind = self->fields[i]; @@ -76,6 +76,16 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code, } } +/* Insert a raw field value VALUE into all fields in SELF->fields. + The least significant bit goes in the final field. */ + +static void +insert_all_fields (const aarch64_operand *self, aarch64_insn *code, + aarch64_insn value) +{ + return insert_all_fields_after (self, 0, code, value); +} + /* Operand inserters. */ /* Insert nothing. */ @@ -1595,6 +1605,21 @@ aarch64_ins_x0_to_x30 (const aarch64_operand *self, return true; } +/* Insert an indexed register, with the first field being the register + number and the remaining fields being the index. */ +bool +aarch64_ins_simple_index (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int bias = get_operand_specific_data (self); + insert_field (self->fields[0], code, info->reglane.regno - bias, 0); + insert_all_fields_after (self, 1, code, info->reglane.index); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index f74cb718f3e..4cc48dfdcb6 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -110,6 +110,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30); +AARCH64_DECL_OPD_INSERTER (ins_simple_index); #undef AARCH64_DECL_OPD_INSERTER diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index b367a77fc00..5210db3b008 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -169,7 +169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx00xxxxxxxxxx mov. */ - return 2490; + return 2499; } else { @@ -177,7 +177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2488; + return 2497; } } else @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2491; + return 2500; } else { @@ -196,7 +196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2489; + return 2498; } } } @@ -221,7 +221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx00xxxxxxxxxx mov. */ - return 2486; + return 2495; } else { @@ -229,7 +229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2484; + return 2493; } } else @@ -240,7 +240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2487; + return 2496; } else { @@ -248,7 +248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2485; + return 2494; } } } @@ -275,7 +275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2424; + return 2433; } else { @@ -283,7 +283,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2425; + return 2434; } } else @@ -294,7 +294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2448; + return 2457; } else { @@ -302,7 +302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2449; + return 2458; } } } @@ -316,7 +316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2440; + return 2449; } else { @@ -324,7 +324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2441; + return 2450; } } else @@ -335,7 +335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2432; + return 2441; } else { @@ -343,7 +343,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2433; + return 2442; } } } @@ -360,7 +360,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2456; + return 2465; } else { @@ -368,7 +368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2457; + return 2466; } } else @@ -379,7 +379,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2480; + return 2489; } else { @@ -387,7 +387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2481; + return 2490; } } } @@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2472; + return 2481; } else { @@ -409,7 +409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2473; + return 2482; } } else @@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2464; + return 2473; } else { @@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2465; + return 2474; } } } @@ -492,7 +492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2420; + return 2429; } else { @@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2421; + return 2430; } } else @@ -511,7 +511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2444; + return 2453; } else { @@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2445; + return 2454; } } } @@ -533,7 +533,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2436; + return 2445; } else { @@ -541,7 +541,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2437; + return 2446; } } else @@ -552,7 +552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2428; + return 2437; } else { @@ -560,7 +560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2429; + return 2438; } } } @@ -577,7 +577,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2452; + return 2461; } else { @@ -585,7 +585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2453; + return 2462; } } else @@ -596,7 +596,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2476; + return 2485; } else { @@ -604,7 +604,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2477; + return 2486; } } } @@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2468; + return 2477; } else { @@ -626,7 +626,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2469; + return 2478; } } else @@ -637,7 +637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2460; + return 2469; } else { @@ -645,7 +645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2461; + return 2470; } } } @@ -713,7 +713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2504; + return 2518; } else { @@ -721,7 +721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2505; + return 2519; } } else @@ -732,7 +732,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2528; + return 2542; } else { @@ -740,7 +740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2529; + return 2543; } } } @@ -754,7 +754,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2520; + return 2534; } else { @@ -762,7 +762,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2521; + return 2535; } } else @@ -773,7 +773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2512; + return 2526; } else { @@ -781,7 +781,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2513; + return 2527; } } } @@ -798,7 +798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2536; + return 2550; } else { @@ -806,7 +806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2537; + return 2551; } } else @@ -817,7 +817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2560; + return 2574; } else { @@ -825,7 +825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2561; + return 2575; } } } @@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2552; + return 2566; } else { @@ -847,7 +847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2553; + return 2567; } } else @@ -858,7 +858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2544; + return 2558; } else { @@ -866,7 +866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2545; + return 2559; } } } @@ -930,7 +930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2500; + return 2514; } else { @@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2501; + return 2515; } } else @@ -949,7 +949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2524; + return 2538; } else { @@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2525; + return 2539; } } } @@ -971,7 +971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2516; + return 2530; } else { @@ -979,7 +979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2517; + return 2531; } } else @@ -990,7 +990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2508; + return 2522; } else { @@ -998,7 +998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2509; + return 2523; } } } @@ -1015,7 +1015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2532; + return 2546; } else { @@ -1023,7 +1023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2533; + return 2547; } } else @@ -1034,7 +1034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2556; + return 2570; } else { @@ -1042,7 +1042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2557; + return 2571; } } } @@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2548; + return 2562; } else { @@ -1064,7 +1064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2549; + return 2563; } } else @@ -1075,7 +1075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2540; + return 2554; } else { @@ -1083,7 +1083,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2541; + return 2555; } } } @@ -1175,7 +1175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2426; + return 2435; } else { @@ -1183,7 +1183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2450; + return 2459; } } else @@ -1194,7 +1194,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2442; + return 2451; } else { @@ -1202,7 +1202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2434; + return 2443; } } } @@ -1216,7 +1216,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2458; + return 2467; } else { @@ -1224,7 +1224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2482; + return 2491; } } else @@ -1235,7 +1235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2474; + return 2483; } else { @@ -1243,7 +1243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2466; + return 2475; } } } @@ -1269,7 +1269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2427; + return 2436; } else { @@ -1277,7 +1277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2451; + return 2460; } } else @@ -1288,7 +1288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2443; + return 2452; } else { @@ -1296,7 +1296,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2435; + return 2444; } } } @@ -1310,7 +1310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2459; + return 2468; } else { @@ -1318,7 +1318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2483; + return 2492; } } else @@ -1329,7 +1329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2475; + return 2484; } else { @@ -1337,7 +1337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2467; + return 2476; } } } @@ -1401,7 +1401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2422; + return 2431; } else { @@ -1409,7 +1409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2423; + return 2432; } } else @@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2446; + return 2455; } else { @@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2447; + return 2456; } } } @@ -1442,7 +1442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2438; + return 2447; } else { @@ -1450,7 +1450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2439; + return 2448; } } else @@ -1461,7 +1461,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2430; + return 2439; } else { @@ -1469,7 +1469,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2431; + return 2440; } } } @@ -1486,7 +1486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2454; + return 2463; } else { @@ -1494,7 +1494,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2455; + return 2464; } } else @@ -1505,7 +1505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2478; + return 2487; } else { @@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2479; + return 2488; } } } @@ -1527,7 +1527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2470; + return 2479; } else { @@ -1535,7 +1535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2471; + return 2480; } } else @@ -1546,7 +1546,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2462; + return 2471; } else { @@ -1554,7 +1554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2463; + return 2472; } } } @@ -1594,13 +1594,150 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 30) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx0xxxx + fmopa. */ + return 2367; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx1xxxx + fmops. */ + return 2370; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx0xxxxxxxxxxxxxxxx + sel. */ + return 2512; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx1xxxxxxxxxxxxxxxx + sel. */ + return 2513; + } + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx000xxxxxxxxx0xxx + st1b. */ + return 2520; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx010xxxxxxxxx0xxx + st1w. */ + return 2544; + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx001xxxxxxxxx0xxx + st1h. */ + return 2536; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx011xxxxxxxxx0xxx + st1d. */ + return 2528; + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx000xxxxxxxxx1xxx + stnt1b. */ + return 2552; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx010xxxxxxxxx1xxx + stnt1w. */ + return 2576; + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx001xxxxxxxxx1xxx + stnt1h. */ + return 2568; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx011xxxxxxxxx1xxx + stnt1d. */ + return 2560; + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100001001xxxxx0xxxxxxxxxxxxxxx + str. */ + return 2414; + } + } + else { if (((word >> 3) & 0x1) == 0) { @@ -1610,17 +1747,17 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx000xxxxxxxxx0xxx + xx100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2506; + return 2521; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx010xxxxxxxxx0xxx + xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2530; + return 2545; } } else @@ -1629,17 +1766,17 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx001xxxxxxxxx0xxx + xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2522; + return 2537; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx011xxxxxxxxx0xxx + xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2514; + return 2529; } } } @@ -1651,17 +1788,17 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx000xxxxxxxxx1xxx + xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2538; + return 2553; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx010xxxxxxxxx1xxx + xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2562; + return 2577; } } else @@ -1670,129 +1807,25 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx001xxxxxxxxx1xxx + xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2554; + return 2569; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0x00001001xxxxx011xxxxxxxxx1xxx + xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2546; + return 2561; } } } } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1x00001001xxxxx0xxxxxxxxxxxxxxx - str. */ - return 2414; - } } else { - if (((word >> 3) & 0x1) == 0) - { - if (((word >> 13) & 0x1) == 0) - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx100xxxxxxxxx0xxx - st1b. */ - return 2507; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx110xxxxxxxxx0xxx - st1w. */ - return 2531; - } - } - else - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx101xxxxxxxxx0xxx - st1h. */ - return 2523; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx111xxxxxxxxx0xxx - st1d. */ - return 2515; - } - } - } - else - { - if (((word >> 13) & 0x1) == 0) - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx100xxxxxxxxx1xxx - stnt1b. */ - return 2539; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx110xxxxxxxxx1xxx - stnt1w. */ - return 2563; - } - } - else - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx101xxxxxxxxx1xxx - stnt1h. */ - return 2555; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001001xxxxx111xxxxxxxxx1xxx - stnt1d. */ - return 2547; - } - } - } - } - } - else - { - if (((word >> 4) & 0x1) == 0) - { - if (((word >> 29) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001101xxxxxxxxxxxxxxxx0xxxx - fmopa. */ - return 2367; - } - else + if (((word >> 4) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -1800,17 +1833,6 @@ aarch64_opcode_lookup_1 (uint32_t word) umopa. */ return 2380; } - } - else - { - if (((word >> 29) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001101xxxxxxxxxxxxxxxx1xxxx - fmops. */ - return 2370; - } else { /* 33222222222211111111110000000000 @@ -1821,211 +1843,211 @@ aarch64_opcode_lookup_1 (uint32_t word) } } } - } - else - { - if (((word >> 23) & 0x1) == 0) + else { - if (((word >> 3) & 0x1) == 0) - { - if (((word >> 13) & 0x1) == 0) - { - if (((word >> 14) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx000xxxxxxxxx0xxx - st1b. */ - return 2502; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx100xxxxxxxxx0xxx - st1b. */ - return 2503; - } - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx010xxxxxxxxx0xxx - st1w. */ - return 2526; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx110xxxxxxxxx0xxx - st1w. */ - return 2527; - } - } - } - else - { - if (((word >> 14) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx001xxxxxxxxx0xxx - st1h. */ - return 2518; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx101xxxxxxxxx0xxx - st1h. */ - return 2519; - } - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx011xxxxxxxxx0xxx - st1d. */ - return 2510; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx111xxxxxxxxx0xxx - st1d. */ - return 2511; - } - } - } - } - else + if (((word >> 23) & 0x1) == 0) { - if (((word >> 13) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx000xxxxxxxxx1xxx - stnt1b. */ - return 2534; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx000xxxxxxxxx0xxx + st1b. */ + return 2516; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx100xxxxxxxxx0xxx + st1b. */ + return 2517; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx100xxxxxxxxx1xxx - stnt1b. */ - return 2535; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx010xxxxxxxxx0xxx + st1w. */ + return 2540; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx110xxxxxxxxx0xxx + st1w. */ + return 2541; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx010xxxxxxxxx1xxx - stnt1w. */ - return 2558; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx001xxxxxxxxx0xxx + st1h. */ + return 2532; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx101xxxxxxxxx0xxx + st1h. */ + return 2533; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx110xxxxxxxxx1xxx - stnt1w. */ - return 2559; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx011xxxxxxxxx0xxx + st1d. */ + return 2524; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx111xxxxxxxxx0xxx + st1d. */ + return 2525; + } } } } else { - if (((word >> 14) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx001xxxxxxxxx1xxx - stnt1h. */ - return 2550; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx000xxxxxxxxx1xxx + stnt1b. */ + return 2548; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx100xxxxxxxxx1xxx + stnt1b. */ + return 2549; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx101xxxxxxxxx1xxx - stnt1h. */ - return 2551; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx010xxxxxxxxx1xxx + stnt1w. */ + return 2572; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx110xxxxxxxxx1xxx + stnt1w. */ + return 2573; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx011xxxxxxxxx1xxx - stnt1d. */ - return 2542; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx001xxxxxxxxx1xxx + stnt1h. */ + return 2564; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx101xxxxxxxxx1xxx + stnt1h. */ + return 2565; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001011xxxxx111xxxxxxxxx1xxx - stnt1d. */ - return 2543; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx011xxxxxxxxx1xxx + stnt1d. */ + return 2556; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001011xxxxx111xxxxxxxxx1xxx + stnt1d. */ + return 2557; + } } } } } - } - else - { - if (((word >> 4) & 0x1) == 0) + else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00001111xxxxxxxxxxxxxxxx0xxxx - umopa. */ - return 2381; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001111xxxxxxxxxxxxxxxx0xxxx + umopa. */ + return 2381; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100001111xxxxxxxxxxxxxxxx0xxxx + st1q. */ + return 2407; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1x00001111xxxxxxxxxxxxxxxx0xxxx - st1q. */ - return 2407; + xx100001111xxxxxxxxxxxxxxxx1xxxx + umops. */ + return 2383; } } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001111xxxxxxxxxxxxxxxx1xxxx - umops. */ - return 2383; - } } } } @@ -4392,7 +4414,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2604; + return 2626; } else { @@ -4400,7 +4422,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2612; + return 2634; } } else @@ -4411,7 +4433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2608; + return 2630; } else { @@ -4419,7 +4441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2615; + return 2637; } } } @@ -4457,7 +4479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2664; + return 2686; } else { @@ -4465,7 +4487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2670; + return 2692; } } else @@ -4476,7 +4498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2667; + return 2689; } else { @@ -4484,7 +4506,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2673; + return 2695; } } } @@ -4498,7 +4520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2688; + return 2710; } else { @@ -4506,7 +4528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2694; + return 2716; } } else @@ -4517,7 +4539,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2691; + return 2713; } else { @@ -4525,7 +4547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2697; + return 2719; } } } @@ -4542,7 +4564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2676; + return 2698; } else { @@ -4550,7 +4572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2682; + return 2704; } } else @@ -4561,7 +4583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2679; + return 2701; } else { @@ -4569,7 +4591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2685; + return 2707; } } } @@ -4583,7 +4605,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2700; + return 2722; } else { @@ -4591,7 +4613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2706; + return 2728; } } else @@ -4602,7 +4624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2703; + return 2725; } else { @@ -4610,7 +4632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2709; + return 2731; } } } @@ -4675,7 +4697,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2605; + return 2627; } else { @@ -4683,7 +4705,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2613; + return 2635; } } else @@ -4694,7 +4716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2609; + return 2631; } else { @@ -4702,7 +4724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2616; + return 2638; } } } @@ -4740,7 +4762,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2665; + return 2687; } else { @@ -4748,7 +4770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2671; + return 2693; } } else @@ -4759,7 +4781,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2668; + return 2690; } else { @@ -4767,7 +4789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2674; + return 2696; } } } @@ -4781,7 +4803,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2689; + return 2711; } else { @@ -4789,7 +4811,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2695; + return 2717; } } else @@ -4800,7 +4822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2692; + return 2714; } else { @@ -4808,7 +4830,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2698; + return 2720; } } } @@ -4825,7 +4847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2677; + return 2699; } else { @@ -4833,7 +4855,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2683; + return 2705; } } else @@ -4844,7 +4866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2680; + return 2702; } else { @@ -4852,7 +4874,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2686; + return 2708; } } } @@ -4866,7 +4888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2701; + return 2723; } else { @@ -4874,7 +4896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2707; + return 2729; } } else @@ -4885,7 +4907,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2704; + return 2726; } else { @@ -4893,7 +4915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2710; + return 2732; } } } @@ -4961,7 +4983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2607; + return 2629; } else { @@ -4969,7 +4991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2614; + return 2636; } } else @@ -4978,7 +5000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2611; + return 2633; } } else @@ -4989,7 +5011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2606; + return 2628; } else { @@ -4997,7 +5019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2610; + return 2632; } } } @@ -5059,7 +5081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2666; + return 2688; } else { @@ -5067,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2760; + return 2782; } } else @@ -5078,7 +5100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2672; + return 2694; } else { @@ -5086,7 +5108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2762; + return 2784; } } } @@ -5100,7 +5122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2669; + return 2691; } else { @@ -5108,7 +5130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2761; + return 2783; } } else @@ -5117,7 +5139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2675; + return 2697; } } } @@ -5133,7 +5155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2690; + return 2712; } else { @@ -5141,7 +5163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2766; + return 2788; } } else @@ -5152,7 +5174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2696; + return 2718; } else { @@ -5160,7 +5182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2768; + return 2790; } } } @@ -5174,7 +5196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2693; + return 2715; } else { @@ -5182,7 +5204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2767; + return 2789; } } else @@ -5191,7 +5213,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2699; + return 2721; } } } @@ -5210,7 +5232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2678; + return 2700; } else { @@ -5218,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2763; + return 2785; } } else @@ -5229,7 +5251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2684; + return 2706; } else { @@ -5237,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2765; + return 2787; } } } @@ -5251,7 +5273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2681; + return 2703; } else { @@ -5259,7 +5281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2764; + return 2786; } } else @@ -5268,7 +5290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2687; + return 2709; } } } @@ -5284,7 +5306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2702; + return 2724; } else { @@ -5292,7 +5314,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2769; + return 2791; } } else @@ -5303,7 +5325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2708; + return 2730; } else { @@ -5311,7 +5333,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2771; + return 2793; } } } @@ -5325,7 +5347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2705; + return 2727; } else { @@ -5333,7 +5355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2770; + return 2792; } } else @@ -5342,7 +5364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2711; + return 2733; } } } @@ -5715,7 +5737,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2789; + return 2811; } else { @@ -5733,7 +5755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2792; + return 2814; } } } @@ -5813,7 +5835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2602; + return 2624; } else { @@ -5821,7 +5843,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2603; + return 2625; } } else @@ -5928,7 +5950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2794; + return 2816; } } } @@ -5944,7 +5966,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2791; + return 2813; } else { @@ -5989,7 +6011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2601; + return 2623; } else { @@ -6083,7 +6105,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2793; + return 2815; } } } @@ -6213,7 +6235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2795; + return 2817; } } } @@ -6229,7 +6251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2790; + return 2812; } else { @@ -7071,7 +7093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2621; + return 2643; } } } @@ -7145,7 +7167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2622; + return 2644; } } } @@ -9819,7 +9841,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2620; + return 2642; } } } @@ -11523,7 +11545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2649; + return 2671; } } else @@ -11766,7 +11788,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2625; + return 2647; } else { @@ -11774,7 +11796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2626; + return 2648; } } else @@ -12006,7 +12028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2646; + return 2668; } else { @@ -12027,7 +12049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2653; + return 2675; } else { @@ -12035,7 +12057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2652; + return 2674; } } else @@ -12090,7 +12112,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2645; + return 2667; } else { @@ -12102,7 +12124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2651; + return 2673; } else { @@ -12110,7 +12132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2650; + return 2672; } } else @@ -12161,7 +12183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2629; + return 2651; } else { @@ -12169,7 +12191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2630; + return 2652; } } else @@ -12528,7 +12550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2623; + return 2645; } else { @@ -12561,7 +12583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2647; + return 2669; } else { @@ -12591,7 +12613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2624; + return 2646; } else { @@ -12720,7 +12742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2633; + return 2655; } else { @@ -12730,7 +12752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2635; + return 2657; } else { @@ -12738,7 +12760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2637; + return 2659; } } } @@ -12750,7 +12772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2634; + return 2656; } else { @@ -12760,7 +12782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2636; + return 2658; } else { @@ -12768,7 +12790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2638; + return 2660; } } } @@ -13827,7 +13849,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2617; + return 2639; } else { @@ -13835,7 +13857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2619; + return 2641; } } else @@ -13844,7 +13866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2618; + return 2640; } } } @@ -15340,7 +15362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2627; + return 2649; } else { @@ -15348,7 +15370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2628; + return 2650; } } } @@ -15722,7 +15744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2631; + return 2653; } else { @@ -15730,7 +15752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2632; + return 2654; } } } @@ -16069,11 +16091,220 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx1xxxxx01xxxxxxxxxxxxxx - psel. */ - return 2418; + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01xxxxxxxxx0xxxx + psel. */ + return 2418; + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x000xxxxx10xxx + whilege. */ + return 2578; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x000xxxxx11xxx + whilegt. */ + return 2579; + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010100xxxxx1xxx0 + whilege. */ + return 2420; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010100xxxxx1xxx1 + whilegt. */ + return 2421; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx011100xxxxx1xxxx + pext. */ + return 2509; + } + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x010xxxxx10xxx + whilehs. */ + return 2581; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x010xxxxx11xxx + whilehi. */ + return 2580; + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010110xxxxx1xxx0 + whilehs. */ + return 2423; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010110xxxxx1xxx1 + whilehi. */ + return 2422; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx011110xxxxx1xxxx + ptrue. */ + return 2511; + } + } + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x001xxxxx10xxx + whilelt. */ + return 2585; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x001xxxxx11xxx + whilele. */ + return 2582; + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010101xxxxx1xxx0 + whilelt. */ + return 2427; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx010101xxxxx1xxx1 + whilele. */ + return 2424; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx011101xxxxx1xxxx + pext. */ + return 2510; + } + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x011xxxxx10xxx + whilelo. */ + return 2583; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x011xxxxx11xxx + whilels. */ + return 2584; + } + } + else + { + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x111xxxxx1xxx0 + whilelo. */ + return 2425; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx1xxxxx01x111xxxxx1xxx1 + whilels. */ + return 2426; + } + } + } + } + } } else { @@ -17175,7 +17406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2648; + return 2670; } } else @@ -17622,90 +17853,123 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 9) & 0x1) == 0) { - if (((word >> 17) & 0x1) == 0) + if (((word >> 16) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - if (((word >> 19) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10000010xxxxxxxxxxxxxx - cntp. */ - return 1365; - } - else + if (((word >> 18) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10000010xxxx0xxxxxxxxx + cntp. */ + return 1365; + } + else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10100010x000xxxxxxxxxx - sqincp. */ - return 1874; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10100010x0000xxxxxxxxx + sqincp. */ + return 1874; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10100010x1000xxxxxxxxx + wrffr. */ + return 2048; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10100010x100xxxxxxxxxx - wrffr. */ - return 2048; + 001001x1xx10100010xx100xxxxxxxxx + sqincp. */ + return 1876; } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10100010xx10xxxxxxxxxx + 001001x1xx10100010xxx10xxxxxxxxx sqincp. */ - return 1876; + return 1875; + } + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x10010x00x0xxxxxxxxx + incp. */ + return 1503; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x10010x10x0xxxxxxxxx + setffr. */ + return 1841; } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10100010xxx1xxxxxxxxxx - sqincp. */ - return 1875; + 001001x1xx10x10010xx1x0xxxxxxxxx + incp. */ + return 1504; } } } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10x10010x00xxxxxxxxxxx - incp. */ - return 1503; + 001001x1xx10xx1010xx000xxxxxxxxx + sqdecp. */ + return 1860; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10x10010x10xxxxxxxxxxx - setffr. */ - return 1841; + 001001x1xx10xx1010xx100xxxxxxxxx + sqdecp. */ + return 1862; } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10x10010xx1xxxxxxxxxxx - incp. */ - return 1504; + 001001x1xx10xx1010xxx10xxxxxxxxx + sqdecp. */ + return 1861; } } } @@ -17715,115 +17979,93 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 11) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx1010xx00xxxxxxxxxx - sqdecp. */ - return 1860; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx1010xx10xxxxxxxxxx - sqdecp. */ - return 1862; - } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx1010xxx1xxxxxxxxxx - sqdecp. */ - return 1861; - } - } - } - else - { - if (((word >> 10) & 0x1) == 0) - { - if (((word >> 11) & 0x1) == 0) - { - if (((word >> 17) & 0x1) == 0) - { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10x00110xx00xxxxxxxxxx - uqincp. */ - return 2023; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x00110xx000xxxxxxxxx + uqincp. */ + return 2023; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x10110xx000xxxxxxxxx + decp. */ + return 1378; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10x10110xx00xxxxxxxxxx - decp. */ - return 1378; + 001001x1xx10xx1110xx000xxxxxxxxx + uqdecp. */ + return 2009; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx1110xx00xxxxxxxxxx - uqdecp. */ - return 2009; - } - } - else - { - if (((word >> 17) & 0x1) == 0) - { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10x00110xx10xxxxxxxxxx - uqincp. */ - return 2024; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x00110xx100xxxxxxxxx + uqincp. */ + return 2024; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10x10110xx100xxxxxxxxx + decp. */ + return 1379; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10x10110xx10xxxxxxxxxx - decp. */ - return 1379; + 001001x1xx10xx1110xx100xxxxxxxxx + uqdecp. */ + return 2010; } } + } + else + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10xx0110xxx10xxxxxxxxx + uqincp. */ + return 2025; + } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 001001x1xx10xx1110xx10xxxxxxxxxx + 001001x1xx10xx1110xxx10xxxxxxxxx uqdecp. */ - return 2010; + return 2011; } } } - else - { - if (((word >> 17) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx0110xxx1xxxxxxxxxx - uqincp. */ - return 2025; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 001001x1xx10xx1110xxx1xxxxxxxxxx - uqdecp. */ - return 2011; - } - } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 001001x1xx10xxxx10xxxx1xxxxxxxxx + cntp. */ + return 2428; } } else @@ -18525,7 +18767,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2784; + return 2806; } else { @@ -19105,7 +19347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2712; + return 2734; } else { @@ -19113,7 +19355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2714; + return 2736; } } else @@ -19124,7 +19366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2718; + return 2740; } else { @@ -19132,7 +19374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2720; + return 2742; } } } @@ -19146,7 +19388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2715; + return 2737; } else { @@ -19154,7 +19396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2717; + return 2739; } } else @@ -19165,7 +19407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2721; + return 2743; } else { @@ -19173,7 +19415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2723; + return 2745; } } } @@ -19190,7 +19432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2736; + return 2758; } else { @@ -19198,7 +19440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2738; + return 2760; } } else @@ -19209,7 +19451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2742; + return 2764; } else { @@ -19217,7 +19459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2744; + return 2766; } } } @@ -19231,7 +19473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2739; + return 2761; } else { @@ -19239,7 +19481,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2741; + return 2763; } } else @@ -19250,7 +19492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2745; + return 2767; } else { @@ -19258,7 +19500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2747; + return 2769; } } } @@ -19278,7 +19520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2724; + return 2746; } else { @@ -19286,7 +19528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2726; + return 2748; } } else @@ -19297,7 +19539,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2730; + return 2752; } else { @@ -19305,7 +19547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2732; + return 2754; } } } @@ -19319,7 +19561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2727; + return 2749; } else { @@ -19327,7 +19569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2729; + return 2751; } } else @@ -19338,7 +19580,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2733; + return 2755; } else { @@ -19346,7 +19588,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2735; + return 2757; } } } @@ -19363,7 +19605,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2748; + return 2770; } else { @@ -19371,7 +19613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2750; + return 2772; } } else @@ -19382,7 +19624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2754; + return 2776; } else { @@ -19390,7 +19632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2756; + return 2778; } } } @@ -19404,7 +19646,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2751; + return 2773; } else { @@ -19412,7 +19654,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2753; + return 2775; } } else @@ -19423,7 +19665,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2757; + return 2779; } else { @@ -19431,7 +19673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2759; + return 2781; } } } @@ -19465,7 +19707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2713; + return 2735; } else { @@ -19473,7 +19715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2772; + return 2794; } } else @@ -19484,7 +19726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2719; + return 2741; } else { @@ -19492,7 +19734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2774; + return 2796; } } } @@ -19506,7 +19748,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2716; + return 2738; } else { @@ -19514,7 +19756,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2773; + return 2795; } } else @@ -19523,7 +19765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2722; + return 2744; } } } @@ -19539,7 +19781,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2737; + return 2759; } else { @@ -19547,7 +19789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2778; + return 2800; } } else @@ -19558,7 +19800,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2743; + return 2765; } else { @@ -19566,7 +19808,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2780; + return 2802; } } } @@ -19580,7 +19822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2740; + return 2762; } else { @@ -19588,7 +19830,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2779; + return 2801; } } else @@ -19597,7 +19839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2746; + return 2768; } } } @@ -19616,7 +19858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2725; + return 2747; } else { @@ -19624,7 +19866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2775; + return 2797; } } else @@ -19635,7 +19877,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2731; + return 2753; } else { @@ -19643,7 +19885,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2777; + return 2799; } } } @@ -19657,7 +19899,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2728; + return 2750; } else { @@ -19665,7 +19907,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2776; + return 2798; } } else @@ -19674,7 +19916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2734; + return 2756; } } } @@ -19690,7 +19932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2749; + return 2771; } else { @@ -19698,7 +19940,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2781; + return 2803; } } else @@ -19709,7 +19951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2755; + return 2777; } else { @@ -19717,7 +19959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2783; + return 2805; } } } @@ -19731,7 +19973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2752; + return 2774; } else { @@ -19739,7 +19981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2782; + return 2804; } } else @@ -19748,7 +19990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2758; + return 2780; } } } @@ -19915,7 +20157,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2639; + return 2661; } } } @@ -19948,7 +20190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2565; + return 2587; } } else @@ -20022,7 +20264,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2641; + return 2663; } } } @@ -20055,7 +20297,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2642; + return 2664; } } else @@ -20102,7 +20344,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2572; + return 2594; } else { @@ -20110,7 +20352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2574; + return 2596; } } else @@ -20121,7 +20363,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2576; + return 2598; } else { @@ -20135,7 +20377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2577; + return 2599; } else { @@ -20143,7 +20385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2570; + return 2592; } } else @@ -20152,7 +20394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2579; + return 2601; } } else @@ -20165,7 +20407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2578; + return 2600; } else { @@ -20173,7 +20415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2583; + return 2605; } } else @@ -20182,7 +20424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2580; + return 2602; } } } @@ -20363,7 +20605,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2564; + return 2586; } } else @@ -20394,7 +20636,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2640; + return 2662; } else { @@ -20413,7 +20655,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2656; + return 2678; } else { @@ -20423,7 +20665,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2654; + return 2676; } else { @@ -20433,7 +20675,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2661; + return 2683; } else { @@ -20441,7 +20683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2660; + return 2682; } } } @@ -21025,7 +21267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2657; + return 2679; } else { @@ -21033,7 +21275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2658; + return 2680; } } } @@ -21351,7 +21593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2575; + return 2597; } } else @@ -21962,7 +22204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2568; + return 2590; } } } @@ -22014,7 +22256,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2581; + return 2603; } } } @@ -22257,7 +22499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2571; + return 2593; } } else @@ -22333,7 +22575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2584; + return 2606; } } else @@ -23159,7 +23401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2569; + return 2591; } } else @@ -23191,7 +23433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2582; + return 2604; } } else @@ -23431,7 +23673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2573; + return 2595; } } else @@ -23463,7 +23705,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2587; + return 2609; } else { @@ -23471,7 +23713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2591; + return 2613; } } } @@ -23493,7 +23735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2588; + return 2610; } else { @@ -23501,7 +23743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2592; + return 2614; } } } @@ -23540,7 +23782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2585; + return 2607; } else { @@ -23548,7 +23790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2589; + return 2611; } } else @@ -23570,7 +23812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2586; + return 2608; } else { @@ -23578,7 +23820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2590; + return 2612; } } else @@ -25386,7 +25628,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2593; + return 2615; } else { @@ -25394,7 +25636,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2597; + return 2619; } } else @@ -25416,7 +25658,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2594; + return 2616; } else { @@ -25424,7 +25666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2598; + return 2620; } } else @@ -25930,7 +26172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2595; + return 2617; } else { @@ -25938,7 +26180,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2599; + return 2621; } } } @@ -25960,7 +26202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2596; + return 2618; } else { @@ -25968,7 +26210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2600; + return 2622; } } } @@ -26024,7 +26266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2567; + return 2589; } else { @@ -26032,7 +26274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2566; + return 2588; } } } @@ -26135,7 +26377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2644; + return 2666; } else { @@ -26143,7 +26385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2643; + return 2665; } } else @@ -26154,7 +26396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2655; + return 2677; } else { @@ -26164,7 +26406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2663; + return 2685; } else { @@ -26172,7 +26414,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2662; + return 2684; } } } @@ -26661,24 +26903,24 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) { case 2389: value = 2391; break; /* mov --> mova. */ case 2391: return NULL; /* mova --> NULL. */ - case 2490: value = 2498; break; /* mov --> mova. */ - case 2498: return NULL; /* mova --> NULL. */ - case 2488: value = 2496; break; /* mov --> mova. */ - case 2496: return NULL; /* mova --> NULL. */ - case 2491: value = 2499; break; /* mov --> mova. */ - case 2499: return NULL; /* mova --> NULL. */ - case 2489: value = 2497; break; /* mov --> mova. */ - case 2497: return NULL; /* mova --> NULL. */ + case 2499: value = 2507; break; /* mov --> mova. */ + case 2507: return NULL; /* mova --> NULL. */ + case 2497: value = 2505; break; /* mov --> mova. */ + case 2505: return NULL; /* mova --> NULL. */ + case 2500: value = 2508; break; /* mov --> mova. */ + case 2508: return NULL; /* mova --> NULL. */ + case 2498: value = 2506; break; /* mov --> mova. */ + case 2506: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2486: value = 2494; break; /* mov --> mova. */ - case 2494: return NULL; /* mova --> NULL. */ - case 2484: value = 2492; break; /* mov --> mova. */ - case 2492: return NULL; /* mova --> NULL. */ - case 2487: value = 2495; break; /* mov --> mova. */ - case 2495: return NULL; /* mova --> NULL. */ - case 2485: value = 2493; break; /* mov --> mova. */ - case 2493: return NULL; /* mova --> NULL. */ + case 2495: value = 2503; break; /* mov --> mova. */ + case 2503: return NULL; /* mova --> NULL. */ + case 2493: value = 2501; break; /* mov --> mova. */ + case 2501: return NULL; /* mova --> NULL. */ + case 2496: value = 2504; break; /* mov --> mova. */ + case 2504: return NULL; /* mova --> NULL. */ + case 2494: value = 2502; break; /* mov --> mova. */ + case 2502: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -26700,11 +26942,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2785; break; /* addg --> smax. */ - case 2785: value = 2786; break; /* smax --> umax. */ - case 2786: value = 2787; break; /* umax --> smin. */ - case 2787: value = 2788; break; /* smin --> umin. */ - case 2788: return NULL; /* umin --> NULL. */ + case 19: value = 2807; break; /* addg --> smax. */ + case 2807: value = 2808; break; /* smax --> umax. */ + case 2808: value = 2809; break; /* umax --> smin. */ + case 2809: value = 2810; break; /* smin --> umin. */ + case 2810: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -26862,8 +27104,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2659; break; /* fcvt --> bfcvt. */ - case 2659: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2681; break; /* fcvt --> bfcvt. */ + case 2681: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -27370,10 +27612,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 220: - case 221: - case 226: - case 227: + case 222: + case 223: + case 230: + case 231: + case 232: + case 233: return aarch64_ext_regno (self, info, code, inst, errors); case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -27389,7 +27633,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 237: + case 247: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -27435,10 +27679,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 228: case 236: - case 241: - case 242: + case 244: + case 245: + case 246: + case 251: + case 252: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -27599,35 +27845,42 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sve_index (self, info, code, inst, errors); case 211: case 213: + case 229: return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 214: case 215: case 216: case 217: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 218: case 219: + case 228: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 220: + case 221: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 222: case 224: - case 229: + case 226: + case 237: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 223: case 225: + case 227: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 230: - case 231: - case 232: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); - case 233: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 234: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 235: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_simple_index (self, info, code, inst, errors); case 238: case 239: case 240: + return aarch64_ext_sme_za_array (self, info, code, inst, errors); + case 241: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 242: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 243: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 248: + case 249: + case 250: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 29b12d238e2..a2f69186355 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -168,18 +168,20 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...) return value; } -/* Extract the value of all fields in SELF->fields from instruction CODE. - The least significant bit comes from the final field. */ +/* Extract the value of all fields in SELF->fields after START from + instruction CODE. The least significant bit comes from the final field. */ static aarch64_insn -extract_all_fields (const aarch64_operand *self, aarch64_insn code) +extract_all_fields_after (const aarch64_operand *self, unsigned int start, + aarch64_insn code) { aarch64_insn value; unsigned int i; enum aarch64_field_kind kind; value = 0; - for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) + for (i = start; + i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) { kind = self->fields[i]; value <<= fields[kind].width; @@ -188,6 +190,15 @@ extract_all_fields (const aarch64_operand *self, aarch64_insn code) return value; } +/* Extract the value of all fields in SELF->fields from instruction CODE. + The least significant bit comes from the final field. */ + +static aarch64_insn +extract_all_fields (const aarch64_operand *self, aarch64_insn code) +{ + return extract_all_fields_after (self, 0, code); +} + /* Sign-extend bit I of VALUE. */ static inline uint64_t sign_extend (aarch64_insn value, unsigned i) @@ -2126,6 +2137,20 @@ aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info, info->reg.regno = extract_field (self->fields[0], code, 0); return info->reg.regno <= 30; } + +/* Decode an indexed register, with the first field being the register + number and the remaining fields being the index. */ +bool +aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int bias = get_operand_specific_data (self); + info->reglane.regno = extract_field (self->fields[0], code, 0) + bias; + info->reglane.index = extract_all_fields_after (self, 1, code); + return true; +} /* Bitfields that are commonly used to encode certain operands' information may be partially used as part of the base opcode in some instructions. diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 98b6b371803..6e6c00b1de2 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -134,6 +134,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); +AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index); #undef AARCH64_DECL_OPD_EXTRACTOR diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 1faa900b245..9f2b670c49a 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -240,6 +240,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"}, @@ -250,8 +252,14 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2}, "a list of SVE predicate registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNd3}, "an SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm1_8}, "an indexed SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, @@ -260,6 +268,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 66c9d65d16e..3b4397d0f06 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -99,6 +99,13 @@ const char *const aarch64_sve_prfop_array[16] = { 0 }; +/* Vector length multiples for a predicate-as-counter operand. Used in things + like AARCH64_OPND_SME_VLxN_10. */ +const char *const aarch64_sme_vlxn_array[2] = { + "vlx2", + "vlx4" +}; + /* Helper functions to determine which operand to be used to encode/decode the size:Q fields for AdvSIMD instructions. */ @@ -220,15 +227,22 @@ const aarch64_field fields[] = { 10, 5 }, /* Rt2: in load/store pair instructions. */ { 12, 1 }, /* S: in load/store reg offset instructions. */ { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */ + { 1, 3 }, /* SME_Pdx2: predicate register, multiple of 2, [3:1]. */ { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */ + { 0, 3 }, /* SME_PNd3: PN0-PN7, bits [2:0]. */ + { 5, 3 }, /* SME_PNn3: PN0-PN7, bits [7:5]. */ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ + { 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */ + { 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ { 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ + { 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */ + { 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */ { 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ { 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */ { 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */ @@ -303,6 +317,8 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ + { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ + { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */ { 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */ { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ @@ -1720,6 +1736,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_PNn3_INDEX1: + case AARCH64_OPND_SME_PNn3_INDEX2: + size = get_operand_field_width (get_operand_from_code (type), 1); + if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15, + 0, (1 << size) - 1)) + return 0; + break; + case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; @@ -1736,8 +1760,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_CLASS_SVE_REGLIST: switch (type) { + case AARCH64_OPND_SME_Pdx2: case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Zmx2: + case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx4: num = get_operand_specific_data (&aarch64_operands[type]); @@ -1767,6 +1794,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; + case AARCH64_OPND_SME_PdxN: case AARCH64_OPND_SVE_ZnxN: case AARCH64_OPND_SVE_ZtxN: num = get_opcode_dependent_value (opcode); @@ -1825,6 +1853,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_CLASS_PRED_REG: switch (type) { + case AARCH64_OPND_SME_PNd3: case AARCH64_OPND_SME_PNg3: if (opnd->reg.regno < 8) { @@ -3366,10 +3395,11 @@ static void print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, const char *prefix, struct aarch64_styler *styler) { + const int mask = (prefix[0] == 'p' ? 15 : 31); const int num_regs = opnd->reglist.num_regs; const int stride = opnd->reglist.stride; const int first_reg = opnd->reglist.first_regno; - const int last_reg = (first_reg + (num_regs - 1) * stride) & 0x1f; + const int last_reg = (first_reg + (num_regs - 1) * stride) & mask; const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier); char tb[16]; /* Temporary buffer. */ @@ -3394,9 +3424,9 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, else { const int reg0 = first_reg; - const int reg1 = (first_reg + stride) & 0x1f; - const int reg2 = (first_reg + stride * 2) & 0x1f; - const int reg3 = (first_reg + stride * 3) & 0x1f; + const int reg1 = (first_reg + stride) & mask; + const int reg2 = (first_reg + stride * 2) & mask; + const int reg3 = (first_reg + stride * 3) & mask; switch (num_regs) { @@ -3774,7 +3804,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_PNg4_10: case AARCH64_OPND_SVE_PNn: case AARCH64_OPND_SVE_PNt: + case AARCH64_OPND_SME_PNd3: case AARCH64_OPND_SME_PNg3: + case AARCH64_OPND_SME_PNn: if (opnd->qualifier == AARCH64_OPND_QLF_NIL) snprintf (buf, size, "%s", style_reg (styler, "pn%d", opnd->reg.regno)); @@ -3789,6 +3821,18 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, aarch64_get_qualifier_name (opnd->qualifier))); break; + case AARCH64_OPND_SME_Pdx2: + case AARCH64_OPND_SME_PdxN: + print_register_list (buf, size, opnd, "p", styler); + break; + + case AARCH64_OPND_SME_PNn3_INDEX1: + case AARCH64_OPND_SME_PNn3_INDEX2: + snprintf (buf, size, "%s[%s]", + style_reg (styler, "pn%d", opnd->reglane.regno), + style_imm (styler, "%" PRIi64, opnd->reglane.index)); + break; + case AARCH64_OPND_SVE_Za_5: case AARCH64_OPND_SVE_Za_16: case AARCH64_OPND_SVE_Zd: @@ -3808,6 +3852,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_ZtxN: case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Zmx2: + case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx4: case AARCH64_OPND_SME_Ztx2_STRIDED: @@ -3902,6 +3948,14 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm)); break; + case AARCH64_OPND_SME_VLxN_10: + case AARCH64_OPND_SME_VLxN_13: + enum_value = opnd->imm.value; + assert (enum_value < ARRAY_SIZE (aarch64_sme_vlxn_array)); + snprintf (buf, size, "%s", + style_sub_mnem (styler, aarch64_sme_vlxn_array[enum_value])); + break; + case AARCH64_OPND_CRn: case AARCH64_OPND_CRm: snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 4b9a27b212d..e505786e60e 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -48,15 +48,22 @@ enum aarch64_field_kind FLD_Rt2, FLD_S, FLD_SM3_imm2, + FLD_SME_Pdx2, FLD_SME_Pm, + FLD_SME_PNd3, + FLD_SME_PNn3, FLD_SME_Q, FLD_SME_Rm, FLD_SME_Rv, FLD_SME_V, + FLD_SME_VL_10, + FLD_SME_VL_13, FLD_SME_ZAda_2b, FLD_SME_ZAda_3b, FLD_SME_Zdn2, FLD_SME_Zdn4, + FLD_SME_Zm2, + FLD_SME_Zm4, FLD_SME_Zn2, FLD_SME_Zn4, FLD_SME_ZtT, @@ -131,6 +138,8 @@ enum aarch64_field_kind FLD_cond2, FLD_defgh, FLD_hw, + FLD_imm1_8, + FLD_imm2_8, FLD_imm3_0, FLD_imm3_5, FLD_imm3_10, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index babf5613da9..cff35b127bd 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2138,6 +2138,13 @@ QLF3(S_S,X,X), \ QLF3(S_D,X,X), \ } +#define OP_SVE_VXXU_BHSD \ +{ \ + QLF4(S_B,X,X,NIL), \ + QLF4(S_H,X,X,NIL), \ + QLF4(S_S,X,X,NIL), \ + QLF4(S_D,X,X,NIL), \ +} #define OP_SVE_VZVD_BHS \ { \ QLF4(S_B,P_Z,S_B,S_D), \ @@ -2185,6 +2192,13 @@ QLF3(S_S,P_Z,S_S), \ QLF3(S_D,P_Z,S_D), \ } +#define OP_SVE_V_BHSD \ +{ \ + QLF1(S_B), \ + QLF1(S_H), \ + QLF1(S_S), \ + QLF1(S_D), \ +} #define OP_SVE_V_HSD \ { \ QLF1(S_H), \ @@ -5285,7 +5299,18 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), + /* SME2 extensions to SVE2. */ + SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), + /* SME2 extensions to SME. */ + SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), @@ -5366,6 +5391,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0), + SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0), + SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0), + SME2_INSN ("sel", 0xc1208000, 0xff21e021, sme_size_22, 0, OP4 (SME_Zdnx2, SME_PNg3, SME_Znx2, SME_Zmx2), OP_SVE_VUVV_BHSD, 0, 0), + SME2_INSN ("sel", 0xc1218000, 0xff23e063, sme_size_22, 0, OP4 (SME_Zdnx4, SME_PNg3, SME_Znx4, SME_Zmx4), OP_SVE_VUVV_BHSD, 0, 0), SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0), SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), @@ -5430,6 +5460,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), + SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -6074,6 +6112,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_Zdn2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ F(FLD_SME_Zdn4), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \ + F(FLD_SME_Zm2), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \ + F(FLD_SME_Zm4), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \ F(FLD_SME_Zn2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \ @@ -6100,10 +6142,24 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \ F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \ "an SME horizontal or vertical vector access register") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \ + F(FLD_SME_Pdx2), "a list of SVE predicate registers") \ + Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd), \ + "a list of SVE predicate registers") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ + Y(PRED_REG, regno, "SME_PNd3", 8 << OPD_F_OD_LSB, F(FLD_SME_PNd3), \ + "an SVE predicate-as-counter register") \ Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \ "an SVE predicate-as-counter register") \ + Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \ + "an SVE predicate-as-counter register") \ + Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB, \ + F(FLD_SME_PNn3, FLD_imm1_8), \ + "an indexed SVE predicate-as-counter register") \ + Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB, \ + F(FLD_SME_PNn3, FLD_imm2_8), \ + "an indexed SVE predicate-as-counter register") \ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ @@ -6122,6 +6178,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ + Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ + "VLx2 or VLx4") \ + Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ + "VLx2 or VLx4") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ -- 2.30.2