From 9a07257669a886a6d3b2e87cfc5ca3d2a4f01310 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 09:52:22 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 177e30d91..e18df6efb 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -15,7 +15,10 @@ including simulators and compilers: OpenRISC 1200 took 12 years to mature. A Vector or Packed SIMD ISA to reach stable *general-purpose* auto-vectorisation compiler support has never been achieved in the history of computing, not with the combined resources of ARM, Intel, -AMD, MIPS, Sun Microsystems, SGI, Cray, and many more. Rather: GPUs +AMD, MIPS, Sun Microsystems, SGI, Cray, and many more. (*Hand-crafted +assembler and direct use of intrinsics is the Industry-standard norm +to achieve high-performance optimisation where it matters*). +Rather: GPUs have ultra-specialist compilers (CUDA) that are designed from the ground up to support Vector/SIMD parallelism, and associated standards (SPIR-V, Vulkan, OpenCL) managed by -- 2.30.2