From 9a0f962f334392407e48c0f0fee355333fe0bf57 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 4 Apr 2020 16:40:32 -0400 Subject: [PATCH] Working test_add --- src/soc/decoder/isa/caller.py | 11 ++++++++++- src/soc/decoder/isa/test_caller.py | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index a75dc3fa..24ce2a63 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -78,6 +78,10 @@ class ISACaller: def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) + def prep_namespace(self): + si = yield self.decoder.SI + self.namespace.SI = SelectableInt(si, bits=16) + def call(self, name): function, read_regs, uninit_regs, write_regs = self.instrs[name] input_names = create_args(read_regs | uninit_regs) @@ -86,12 +90,17 @@ class ISACaller: inputs = [] for name in input_names: regnum = yield getattr(self.decoder, name) - print(regnum) + print('reading reg %d' % regnum) inputs.append(self.gpr(regnum)) print(inputs) results = function(self, *inputs) print(results) + output_names = create_args(write_regs) + for name, output in zip(output_names, results): + regnum = yield getattr(self.decoder, name) + print('writing reg %d' % regnum) + self.gpr[regnum] = output def inject(): diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index b958795c..fb227396 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -80,11 +80,13 @@ class DecoderTestCase(FHDLTestCase): initial_regs[3] = 0x1234 initial_regs[2] = 0x4321 with Program(lst) as program: - self.run_test_program(program, initial_regs) + sim = self.run_test_program(program, initial_regs) + self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64)) def run_test_program(self, prog, initial_regs): simulator = self.run_tst(prog, initial_regs) print(simulator.gpr) + return simulator if __name__ == "__main__": unittest.main() -- 2.30.2