From 9a1ea4b90728c19a0141fd9b6ab44a3c5ded5a7c Mon Sep 17 00:00:00 2001 From: Ramana Radhakrishnan Date: Fri, 24 Jun 2011 13:15:08 +0000 Subject: [PATCH] re PR target/49335 (ARM: Invalid assembler generated while compiling C++ code from 'codeblocks') Fix PR target/49335 2011-06-24 Ramana Radhakrishnan PR target/49335 * config/arm/predicates.md (add_operator): New. * config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage in Thumb2. From-SVN: r175375 --- gcc/ChangeLog | 7 +++++++ gcc/config/arm/arm.md | 22 +++++++++++++++------- gcc/config/arm/predicates.md | 3 +++ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f91e1a69c5d..7eb82253333 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-06-24 Ramana Radhakrishnan + + PR target/49335 + * config/arm/predicates.md (add_operator): New. + * config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage + in Thumb2. + 2011-06-24 Andi Kleen * tree-sra.c (type_internals_preclude_sra_p): Add msg diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 431208ef7d2..26291afd615 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8632,28 +8632,36 @@ ;; Patterns to allow combination of arithmetic, cond code and shifts (define_insn "*arith_shiftsi" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" - [(match_operand:SI 4 "s_register_operand" "r,r") - (match_operand:SI 5 "shift_amount_operand" "M,r")]) - (match_operand:SI 2 "s_register_operand" "rk,rk")]))] + [(match_operand:SI 4 "s_register_operand" "r,r,r,r") + (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")]) + (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))] "TARGET_32BIT" "%i1%?\\t%0, %2, %4%S3" [(set_attr "predicable" "yes") (set_attr "shift" "4") - (set_attr "arch" "32,a") - ;; We have to make sure to disable the second alternative if + (set_attr "arch" "a,t2,t2,a") + ;; Thumb2 doesn't allow the stack pointer to be used for + ;; operand1 for all operations other than add and sub. In this case + ;; the minus operation is a candidate for an rsub and hence needs + ;; to be disabled. + ;; We have to make sure to disable the fourth alternative if ;; the shift_operator is MULT, since otherwise the insn will ;; also match a multiply_accumulate pattern and validate_change ;; will allow a replacement of the constant with a register ;; despite the checks done in shift_operator. (set_attr_alternative "insn_enabled" [(const_string "yes") + (if_then_else + (match_operand:SI 1 "add_operator" "") + (const_string "yes") (const_string "no")) + (const_string "yes") (if_then_else (match_operand:SI 3 "mult_operator" "") (const_string "no") (const_string "yes"))]) - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index ec5de6921e7..4bd8af144b4 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -707,3 +707,6 @@ (define_special_predicate "neon_struct_operand" (and (match_code "mem") (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) + +(define_special_predicate "add_operator" + (match_code "plus")) -- 2.30.2