From 9a21bc640188e4078075b9f8e6701853a4f0bbe4 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 16 Mar 2011 14:09:17 -0700 Subject: [PATCH] i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 68 ++++++++++++------------- 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 21ce92c9173..b66359467ec 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -52,6 +52,35 @@ static void guess_execution_size(struct brw_compile *p, } +/** + * Prior to Sandybridge, the SEND instruction accepted non-MRF source + * registers, implicitly moving the operand to a message register. + * + * On Sandybridge, this is no longer the case. This function performs the + * explicit move; it should be called before emitting a SEND instruction. + */ +static void +gen6_resolve_implied_move(struct brw_compile *p, + struct brw_reg *src, + GLuint msg_reg_nr) +{ + struct intel_context *intel = &p->brw->intel; + if (intel->gen != 6) + return; + + if (src->file == BRW_ARCHITECTURE_REGISTER_FILE && src->nr == BRW_ARF_NULL) + return; + + brw_push_insn_state(p); + brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD), + retype(*src, BRW_REGISTER_TYPE_UD)); + brw_pop_insn_state(p); + *src = brw_message_reg(msg_reg_nr); +} + + static void brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg dest) @@ -1966,20 +1995,7 @@ void brw_SAMPLE(struct brw_compile *p, { struct brw_instruction *insn; - /* Sandybridge doesn't have the implied move for SENDs, - * and the first message register index comes from src0. - */ - if (intel->gen >= 6) { - if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE || - src0.nr != BRW_ARF_NULL) { - brw_push_insn_state(p); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0); - brw_pop_insn_state(p); - } - src0 = brw_message_reg(msg_reg_nr); - } + gen6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); insn->header.predicate_control = 0; /* XXX */ @@ -2034,17 +2050,7 @@ void brw_urb_WRITE(struct brw_compile *p, struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; - /* Sandybridge doesn't have the implied move for SENDs, - * and the first message register index comes from src0. - */ - if (intel->gen >= 6) { - brw_push_insn_state(p); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD), - retype(src0, BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); - src0 = brw_message_reg(msg_reg_nr); - } + gen6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); @@ -2154,17 +2160,7 @@ void brw_ff_sync(struct brw_compile *p, struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; - /* Sandybridge doesn't have the implied move for SENDs, - * and the first message register index comes from src0. - */ - if (intel->gen >= 6) { - brw_push_insn_state(p); - brw_set_mask_control( p, BRW_MASK_DISABLE ); - brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD), - retype(src0, BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); - src0 = brw_message_reg(msg_reg_nr); - } + gen6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); brw_set_dest(p, insn, dest); -- 2.30.2