From 9a25363e811c79d58f0e5f95856a58b9ad2d6ab0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Oct 2018 06:07:22 +0100 Subject: [PATCH] add spike_sv page --- 3d_gpu/spike_sv.mdwn | 11 +++++++++++ simple_v_extension/specification.mdwn | 10 ++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 3d_gpu/spike_sv.mdwn diff --git a/3d_gpu/spike_sv.mdwn b/3d_gpu/spike_sv.mdwn new file mode 100644 index 000000000..bc74cd974 --- /dev/null +++ b/3d_gpu/spike_sv.mdwn @@ -0,0 +1,11 @@ +# Simple-V Spike emulator + +Needs riscv-tools, first + +* git clone https://git.libre-riscv.org/git/riscv-isa-sim.git +* cd risc-v-isa-sim +* git checkout -b sv +* cd .. +* git clone https://git.libre-riscv.org/git/riscv-tests.git +* cd risc-tests +* git checkout -b sv diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index c70a86acc..f14039d29 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -731,6 +731,12 @@ scalar RV LOAD operation: srcbase = ireg[rs+i]; return mem[srcbase + imm]; +Whilst LOAD and STORE remain as-is when compared to their scalar +counterparts, the incrementing on the source register (for LOAD) +means that pointers-to-structures can be easily implemented, and +if contiguous offsets are required, those pointers (the contents +of the contiguous source registers) may simply be set up to point +to contiguous locations. ## Compressed Stack LOAD / STORE Instructions @@ -759,8 +765,8 @@ that must be incremented. Pseudo-code follows: if (int_csr[rd].isvec) j++; For C.LDSP, the offset (and loop) multiplier would be 8, and for -C.LQSP it would be 16. Effectively this is a Vector "Unit Stride" -Load instruction. +C.LQSP it would be 16. Effectively this makes C.LWSP etc. a Vector +"Unit Stride" Load instruction. **Note**: It is critical for implementors and compiler writers to note that the **real** target register, x2, is predicated. Ordinarily (with all -- 2.30.2