From 9a378df412997cdced01be24d40515ff7be14cdc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 7 May 2021 12:15:48 +0100 Subject: [PATCH] whoops setup of core.sv_pred_sm/dm not indented and under "if svp64_en" --- src/soc/simple/issuer.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 0305624c..cd347aad 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -723,10 +723,10 @@ class TestIssuerInternal(Elaboratable): # proceed to Decode m.next = "DECODE_SV" - # pass predicate mask bits through to satellite decoders - # TODO: for SIMD this will be *multiple* bits - sync += core.sv_pred_sm.eq(self.srcmask[0]) - sync += core.sv_pred_dm.eq(self.dstmask[0]) + # pass predicate mask bits through to satellite decoders + # TODO: for SIMD this will be *multiple* bits + sync += core.sv_pred_sm.eq(self.srcmask[0]) + sync += core.sv_pred_dm.eq(self.dstmask[0]) # after src/dst step have been updated, we are ready # to decode the instruction -- 2.30.2