From 9a63901fb7b59ae76134fc07126b56f32f014f91 Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Sat, 25 Sep 1993 08:29:59 -0400 Subject: [PATCH] Use WORD_REGISTER_OPERATION and LOAD_EXTEND_OP and delete BYTE_LOADS_{SIGN,ZERO}_EXTEND. From-SVN: r5477 --- gcc/config/a29k/a29k.h | 12 +++++++++--- gcc/config/alpha/alpha.h | 16 +++++++++------- gcc/config/arm/arm.h | 7 +------ gcc/config/clipper/clipper.h | 13 +++++++++---- gcc/config/i960/i960.h | 12 +++++++++--- gcc/config/m88k/m88k.h | 12 +++++++++--- gcc/config/mips/mips.h | 15 +++++++++------ gcc/config/pa/pa.h | 12 +++++++++--- gcc/config/romp/romp.h | 12 +++++++++--- gcc/config/rs6000/rs6000.h | 12 +++++++++--- gcc/config/sh/sh.h | 12 +++++++++--- gcc/config/sparc/sparc.h | 12 +++++++++--- 12 files changed, 100 insertions(+), 47 deletions(-) diff --git a/gcc/config/a29k/a29k.h b/gcc/config/a29k/a29k.h index 062a9eab530..95656cc1b44 100644 --- a/gcc/config/a29k/a29k.h +++ b/gcc/config/a29k/a29k.h @@ -1204,9 +1204,15 @@ extern char *a29k_function_name; manipulate fields. */ #define SLOW_BYTE_ACCESS 0 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Define if the object format being used is COFF or a superset. */ #define OBJECT_FORMAT_COFF diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index 880cece20a1..1758919bb16 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -1221,13 +1221,15 @@ extern char *current_function_name; #define SLOW_BYTE_ACCESS 1 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bits in the register. */ -/* #define BYTE_LOADS_ZERO_EXTEND */ - -/* Define if normal loads of shorter-than-word items from memory sign-extends - the rest of the bits in the register. */ -#define BYTE_LOADS_SIGN_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ad12ecbcdec..e2e06918524 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. - Copyright (C) 1991 Free Software Foundation, Inc. + Copyright (C) 1991, 1993 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). @@ -848,11 +848,6 @@ do \ in one reasonably fast instruction. */ #define MOVE_MAX 4 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. - On the ARM, movhi does a garbage extend. */ -/* #define BYTE_LOADS_ZERO_EXTEND */ - /* Define this if zero-extension is slow (more than one real instruction). On the ARM, it is more than one instruction only if not fetching from memory. */ diff --git a/gcc/config/clipper/clipper.h b/gcc/config/clipper/clipper.h index 054660f2908..06a6ffe00d7 100644 --- a/gcc/config/clipper/clipper.h +++ b/gcc/config/clipper/clipper.h @@ -773,10 +773,15 @@ do \ jumps to the default label instead. */ /* #define CASE_DROPS_THROUGH */ -/* Define this macro if an instruction to load a value narrower than a - word from memory into a register also sign-extends the value to - the whole register. */ -#define BYTE_LOADS_SIGN_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR diff --git a/gcc/config/i960/i960.h b/gcc/config/i960/i960.h index e9544edf152..d76a19f7fe7 100644 --- a/gcc/config/i960/i960.h +++ b/gcc/config/i960/i960.h @@ -1055,9 +1055,15 @@ extern struct rtx_def *legitimize_address (); in one reasonably fast instruction. */ #define MOVE_MAX 16 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is no faster than for words. Defining this results in worse code on the i960. */ diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h index bc6dbeab815..8573f1a62e1 100644 --- a/gcc/config/m88k/m88k.h +++ b/gcc/config/m88k/m88k.h @@ -1508,9 +1508,15 @@ enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS, in one reasonably fast instruction. */ #define MOVE_MAX 8 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Zero if access to memory by bytes is faster. */ #define SLOW_BYTE_ACCESS 1 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e1d74e69c86..11c47bee3a0 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1049,12 +1049,15 @@ do { \ #define PROMOTE_PROTOTYPES -/* Define this macro if an instruction to load a value narrower - than a word from memory into a register also zero-extends the - value to the whole register. */ - -#define BYTE_LOADS_ZERO_EXTEND - +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Standard register usage. */ diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 15d6356ab51..551a6f7b14e 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1367,9 +1367,15 @@ while (0) in one reasonably fast instruction. */ #define MOVE_MAX 8 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 1 diff --git a/gcc/config/romp/romp.h b/gcc/config/romp/romp.h index be5047af2db..c454b5e4a30 100644 --- a/gcc/config/romp/romp.h +++ b/gcc/config/romp/romp.h @@ -1186,9 +1186,15 @@ struct rt_cargs {int gregs, fregs; }; is undesirable. */ #define SLOW_BYTE_ACCESS 1 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 6ebb8577f3a..5949ff64204 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1288,9 +1288,15 @@ struct rs6000_args {int words, fregno, nargs_prototype; }; is undesirable. */ #define SLOW_BYTE_ACCESS 1 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index c889bb09e83..c1fdda99044 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -902,9 +902,15 @@ extern int current_function_anonymous_args; in one reasonably fast instruction. */ #define MOVE_MAX 4 -/* Define if normal loads of shorter-than-word items from sign extends - the rest of the bigs in the register. */ -#define BYTE_LOADS_SIGN_EXTEND 1 +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* Define this if zero-extension is slow (more than one real instruction). On the SH, it's only one instruction */ diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 473180487e9..c615eaf0c53 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1348,9 +1348,15 @@ extern struct rtx_def *legitimize_pic_address (); gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) #endif /* 0 */ -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. For RISC chips, it means that access to memory by bytes is no -- 2.30.2