From 9a8190f066f0d66cfb39ded12493ad1a3c15b0b1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 07:35:56 +0100 Subject: [PATCH] add SDRAM clock output --- src/bsv/peripheral_gen/sdram.py | 1 + src/spec/pinfunctions.py | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py index 58e7c02..ce6ba43 100644 --- a/src/bsv/peripheral_gen/sdram.py +++ b/src/bsv/peripheral_gen/sdram.py @@ -35,6 +35,7 @@ class sdram(PBase): return {'sdrwen': 'ifc_sdram_out.osdr_we_n', 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n', 'sdrcke': 'ifc_sdram_out.osdr_cke', + 'sdrclk': 'ifc_sdram_out.osdr_clock', 'sdrrasn': 'ifc_sdram_out.osdr_ras_n', 'sdrcasn': 'ifc_sdram_out.osdr_cas_n', }.get(pname, '') diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index 80a5129..00d97e4 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -175,7 +175,7 @@ def sdram1(suffix, bank): buspins.append("SDRAD%d+" % i) for i in range(2): buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', + buspins += ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', 'SDRCSn0+'] return (buspins, inout) -- 2.30.2