From 9a8d60da0e6bc416fc53606aae60167506e75c4e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 20 Oct 2019 01:06:49 -0700 Subject: [PATCH] cpu: Apply the ARM TLB rework to the checker CPU. The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU already, but the TLBs are added in the checker CPU as well. Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/cpu/simple/BaseSimpleCPU.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index 6714295d2..f8e2948c9 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -42,11 +42,11 @@ class BaseSimpleCPU(BaseCPU): def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmTLB import ArmTLB + from m5.objects.ArmTLB import ArmITB, ArmDTB self.checker = DummyChecker(workload = self.workload) - self.checker.itb = ArmTLB(size = self.itb.size) - self.checker.dtb = ArmTLB(size = self.dtb.size) + self.checker.itb = ArmITB(size = self.itb.size) + self.checker.dtb = ArmDTB(size = self.dtb.size) else: print("ERROR: Checker only supported under ARM ISA!") exit(1) -- 2.30.2