From 9aa5922d8987dfbc36ca23b2700b884f3a5c1f17 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 6 Jul 2010 16:05:19 +0200 Subject: [PATCH] i386.md (immediate_operand): New mode attribute. 2010-07-06 Uros Bizjak * config/i386/i386.md (immediate_operand): New mode attribute. (pro_epilogue_adjust_stack__1): Macroize insn from pro_epilogue_adjust_stack and pro_epilogue_adjust_stack_rex64 using P mode iterator. (pro_epilogue_adjust_stack_di_2): Rename from pro_epilogue_adjust_stack_rex64_2. * config/i386/i386.c (pro_epilogue_adjust_stack): Update for rename. 2010-07-06 Uros Bizjak * config/i386/i386.md (insv): Call gen_movdi_insv1 or gen_movsi_insv1 through gen_mov_insv_1 function pointer. (fmod3): Call gen_truncxf2_i387_noop_unspec or gen_truncxf2 through gen_truncxf function pointer. (remainder3): Ditto. (cmpstrnsi): Rename cmp_insn function pointer to gen_cmp. (allocate_stack): Call gen_allocate_stack_worker_64 or gen_allocate_stack_worker_32 through gen_allocate_stack_worker function pointer. (probe_stack): Call gen_iordi3 or gen_iorsi3 through gen_ior3 function pointer. 2010-07-06 Uros Bizjak * config/i386/i386.md (*add3_cconly_overflow): Use operand constraint instead of m. From-SVN: r161870 --- gcc/ChangeLog | 40 +++++++++-- gcc/config/i386/i386.c | 8 +-- gcc/config/i386/i386.md | 154 +++++++++++++++++----------------------- 3 files changed, 104 insertions(+), 98 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e25324e765d..b27f23b9966 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,34 @@ +2010-07-06 Uros Bizjak + + * config/i386/i386.md (immediate_operand): New mode attribute. + + (pro_epilogue_adjust_stack__1): Macroize insn from + pro_epilogue_adjust_stack and pro_epilogue_adjust_stack_rex64 + using P mode iterator. + (pro_epilogue_adjust_stack_di_2): Rename from + pro_epilogue_adjust_stack_rex64_2. + + * config/i386/i386.c (pro_epilogue_adjust_stack): Update for rename. + +2010-07-06 Uros Bizjak + + * config/i386/i386.md (insv): Call gen_movdi_insv1 or gen_movsi_insv1 + through gen_mov_insv_1 function pointer. + (fmod3): Call gen_truncxf2_i387_noop_unspec or + gen_truncxf2 through gen_truncxf function pointer. + (remainder3): Ditto. + (cmpstrnsi): Rename cmp_insn function pointer to gen_cmp. + (allocate_stack): Call gen_allocate_stack_worker_64 or + gen_allocate_stack_worker_32 through gen_allocate_stack_worker + function pointer. + (probe_stack): Call gen_iordi3 or gen_iorsi3 through gen_ior3 + function pointer. + +2010-07-06 Uros Bizjak + + * config/i386/i386.md (*add3_cconly_overflow): Use + operand constraint instead of m. + 2010-07-06 Richard Guenther PR middle-end/44828 @@ -79,13 +110,11 @@ (OPTION_MASK_ISA_RDRND_UNSET): Likewise. (OPTION_MASK_ISA_F16C_UNSET): Likewise. (OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_F16C_UNSET. - (ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and - OPT_mf16c. + (ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and OPT_mf16c. (ix86_target_string): Support -mfsgsbase, -mrdrnd and -mf16c. (pta_flags): Add PTA_FSGSBASE, PTA_RDRND and PTA_F16C. (override_options): Handle them. - (ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd - and f16c. + (ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd and f16c. (ix86_builtins): Add IX86_BUILTIN_RDFSBASE32, IX86_BUILTIN_RDFSBASE64, IX86_BUILTIN_RDGSBASE32, IX86_BUILTIN_RDGSBASE64, IX86_BUILTIN_WRFSBASE32, @@ -213,8 +242,7 @@ 2010-07-05 Richard Guenther - * tree-ssa-loop-ivopts.c (rewrite_use_nonlinear_expr): Copy - alias info. + * tree-ssa-loop-ivopts.c (rewrite_use_nonlinear_expr): Copy alias info. 2010-07-05 Richard Guenther diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 0df8e74f574..7dfd7bbdcbe 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -8509,9 +8509,9 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, rtx insn; if (! TARGET_64BIT) - insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_si_1 (dest, src, offset)); else if (x86_64_immediate_operand (offset, DImode)) - insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_di_1 (dest, src, offset)); else { rtx tmp; @@ -8528,8 +8528,8 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, insn = emit_insn (gen_rtx_SET (DImode, tmp, offset)); if (style < 0) RTX_FRAME_RELATED_P (insn) = 1; - insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, tmp, - offset)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_di_2 (dest, src, tmp, + offset)); } if (style >= 0) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 20f222ee536..4170711b918 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -860,6 +860,13 @@ (SI "general_operand") (DI "x86_64_szext_general_operand")]) +;; Immediate operand predicate for integer modes. +(define_mode_attr immediate_operand + [(QI "immediate_operand") + (HI "immediate_operand") + (SI "immediate_operand") + (DI "x86_64_immediate_operand")]) + ;; Operand predicate for shifts. (define_mode_attr shift_operand [(QI "nonimmediate_operand") @@ -6904,7 +6911,7 @@ (compare:CCC (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0") - (match_operand:SWI 2 "" "m")) + (match_operand:SWI 2 "" "")) (match_dup 1))) (clobber (match_scratch:SWI 0 "="))] "ix86_binary_operator_ok (PLUS, mode, operands)" @@ -10339,6 +10346,8 @@ (match_operand 3 "register_operand" ""))] "" { + rtx (*gen_mov_insv_1) (rtx, rtx); + /* Handle insertions to %ah et al. */ if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8) FAIL; @@ -10348,11 +10357,10 @@ if (! ext_register_operand (operands[0], VOIDmode)) FAIL; - if (TARGET_64BIT) - emit_insn (gen_movdi_insv_1 (operands[0], operands[3])); - else - emit_insn (gen_movsi_insv_1 (operands[0], operands[3])); + gen_mov_insv_1 = (TARGET_64BIT + ? gen_movdi_insv_1 : gen_movsi_insv_1); + emit_insn (gen_mov_insv_1 (operands[0], operands[3])); DONE; }) @@ -13039,6 +13047,8 @@ (use (match_operand:MODEF 2 "general_operand" ""))] "TARGET_USE_FANCY_MATH_387" { + rtx (*gen_truncxf) (rtx, rtx); + rtx label = gen_label_rtx (); rtx op1 = gen_reg_rtx (XFmode); @@ -13055,10 +13065,11 @@ /* Truncate the result properly for strict SSE math. */ if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387) - emit_insn (gen_truncxf2 (operands[0], op1)); + gen_truncxf = gen_truncxf2; else - emit_insn (gen_truncxf2_i387_noop_unspec (operands[0], op1)); + gen_truncxf = gen_truncxf2_i387_noop_unspec; + emit_insn (gen_truncxf (operands[0], op1)); DONE; }) @@ -13107,6 +13118,8 @@ (use (match_operand:MODEF 2 "general_operand" ""))] "TARGET_USE_FANCY_MATH_387" { + rtx (*gen_truncxf) (rtx, rtx); + rtx label = gen_label_rtx (); rtx op1 = gen_reg_rtx (XFmode); @@ -13124,10 +13137,11 @@ /* Truncate the result properly for strict SSE math. */ if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387) - emit_insn (gen_truncxf2 (operands[0], op1)); + gen_truncxf = gen_truncxf2; else - emit_insn (gen_truncxf2_i387_noop_unspec (operands[0], op1)); + gen_truncxf = gen_truncxf2_i387_noop_unspec; + emit_insn (gen_truncxf (operands[0], op1)); DONE; }) @@ -15733,13 +15747,12 @@ } else { - rtx (*cmp_insn)(rtx, rtx); + rtx (*gen_cmp) (rtx, rtx); - if (TARGET_64BIT) - cmp_insn = gen_cmpdi_1; - else - cmp_insn = gen_cmpsi_1; - emit_insn (cmp_insn (countreg, countreg)); + gen_cmp = (TARGET_64BIT + ? gen_cmpdi_1 : gen_cmpsi_1); + + emit_insn (gen_cmp (countreg, countreg)); emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align, operands[1], operands[2])); } @@ -16353,79 +16366,37 @@ ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))] ;; ;; in proper program order. -(define_insn "pro_epilogue_adjust_stack_1" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI (match_operand:SI 1 "register_operand" "0,r") - (match_operand:SI 2 "immediate_operand" "i,i"))) - (clobber (reg:CC FLAGS_REG)) - (clobber (mem:BLK (scratch)))] - "!TARGET_64BIT" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOV: - return "mov{l}\t{%1, %0|%0, %1}"; - - case TYPE_ALU: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - if (x86_maybe_negate_const_int (&operands[2], SImode)) - return "sub{l}\t{%2, %0|%0, %2}"; - - return "add{l}\t{%2, %0|%0, %2}"; - - default: - operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); - return "lea{l}\t{%a2, %0|%0, %a2}"; - } -} - [(set (attr "type") - (cond [(and (eq_attr "alternative" "0") - (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) - (const_string "alu") - (match_operand:SI 2 "const0_operand" "") - (const_string "imov") - ] - (const_string "lea"))) - (set (attr "length_immediate") - (cond [(eq_attr "type" "imov") - (const_string "0") - (and (eq_attr "type" "alu") - (match_operand 2 "const128_operand" "")) - (const_string "1") - ] - (const_string "*"))) - (set_attr "mode" "SI")]) -(define_insn "pro_epilogue_adjust_stack_rex64" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (plus:DI (match_operand:DI 1 "register_operand" "0,r") - (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) +(define_insn "pro_epilogue_adjust_stack__1" + [(set (match_operand:P 0 "register_operand" "=r,r") + (plus:P (match_operand:P 1 "register_operand" "0,r") + (match_operand:P 2 "" ","))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] - "TARGET_64BIT" + "" { switch (get_attr_type (insn)) { case TYPE_IMOV: - return "mov{q}\t{%1, %0|%0, %1}"; + return "mov{}\t{%1, %0|%0, %1}"; case TYPE_ALU: gcc_assert (rtx_equal_p (operands[0], operands[1])); - if (x86_maybe_negate_const_int (&operands[2], DImode)) - return "sub{q}\t{%2, %0|%0, %2}"; + if (x86_maybe_negate_const_int (&operands[2], mode)) + return "sub{}\t{%2, %0|%0, %2}"; - return "add{q}\t{%2, %0|%0, %2}"; + return "add{}\t{%2, %0|%0, %2}"; default: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); - return "lea{q}\t{%a2, %0|%0, %a2}"; + return "lea{}\t{%a2, %0|%0, %a2}"; } } [(set (attr "type") (cond [(and (eq_attr "alternative" "0") - (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) (const_string "alu") - (match_operand:DI 2 "const0_operand" "") + (match_operand: 2 "const0_operand" "") (const_string "imov") ] (const_string "lea"))) @@ -16437,9 +16408,9 @@ (const_string "1") ] (const_string "*"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "")]) -(define_insn "pro_epilogue_adjust_stack_rex64_2" +(define_insn "pro_epilogue_adjust_stack_di_2" [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_operand:DI 1 "register_operand" "0,r") (match_operand:DI 3 "immediate_operand" "i,i"))) @@ -16509,12 +16480,15 @@ } else { - x = copy_to_mode_reg (Pmode, operands[1]); + rtx (*gen_allocate_stack_worker) (rtx, rtx); + if (TARGET_64BIT) - x = gen_allocate_stack_worker_64 (x, x); + gen_allocate_stack_worker = gen_allocate_stack_worker_64; else - x = gen_allocate_stack_worker_32 (x, x); - emit_insn (x); + gen_allocate_stack_worker = gen_allocate_stack_worker_32; + + x = copy_to_mode_reg (Pmode, operands[1]); + emit_insn (gen_allocate_stack_worker (x, x)); } emit_move_insn (operands[0], virtual_stack_dynamic_rtx); @@ -16526,10 +16500,12 @@ [(match_operand 0 "memory_operand" "")] "" { - if (GET_MODE (operands[0]) == DImode) - emit_insn (gen_iordi3 (operands[0], operands[0], const0_rtx)); - else - emit_insn (gen_iorsi3 (operands[0], operands[0], const0_rtx)); + rtx (*gen_ior3) (rtx, rtx, rtx); + + gen_ior3 = (GET_MODE (operands[0]) == DImode + ? gen_iordi3 : gen_iorsi3); + + emit_insn (gen_ior3 (operands[0], operands[0], const0_rtx)); DONE; }) @@ -17441,7 +17417,7 @@ [(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 1)))] - { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);") (define_peephole2 [(parallel @@ -17457,7 +17433,7 @@ (set (match_dup 0) (plus:SI (mult:SI (match_dup 0) (match_dup 2)) (match_dup 0)))] - { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);") (define_peephole2 [(parallel @@ -17472,7 +17448,7 @@ [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 1)))] - { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);") (define_peephole2 [(parallel @@ -17489,7 +17465,7 @@ (set (match_dup 0) (plus:DI (mult:DI (match_dup 0) (match_dup 2)) (match_dup 0)))] - { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);") ;; Imul $32bit_imm, mem, reg is vector decoded, while ;; imul $32bit_imm, reg, reg is direct decoded. @@ -17504,7 +17480,7 @@ [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] -"") + "") (define_peephole2 [(match_scratch:SI 3 "r") @@ -17517,7 +17493,7 @@ [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] -"") + "") (define_peephole2 [(match_scratch:SI 3 "r") @@ -17529,9 +17505,10 @@ "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p () && !satisfies_constraint_K (operands[2])" [(set (match_dup 3) (match_dup 1)) - (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2)))) + (parallel [(set (match_dup 0) + (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2)))) (clobber (reg:CC FLAGS_REG))])] -"") + "") ;; imul $8/16bit_imm, regmem, reg is vector decoded. ;; Convert it into imul reg, reg @@ -17903,7 +17880,8 @@ (reg:DI XMM4_REG) (reg:DI XMM5_REG) (reg:DI XMM6_REG) - (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE_LOW)) + (reg:DI XMM7_REG)] + UNSPEC_SSE_PROLOGUE_SAVE_LOW)) (use (match_dup 1)) (use (match_dup 2)) (use (match_dup 3)) -- 2.30.2