From 9aadcc797263fc268fdd9f921ddffa473f56d78a Mon Sep 17 00:00:00 2001 From: Brandon Potter Date: Mon, 15 May 2017 14:03:20 -0500 Subject: [PATCH] syscall_emul, riscv: add override keyword to RISCV Process class Change-Id: I2a146ae57aac3787389997961208474a97e7c155 Reviewed-on: https://gem5-review.googlesource.com/3360 Reviewed-by: Anthony Gutierrez Reviewed-by: Jason Lowe-Power Maintainer: Alec Roelke --- src/arch/riscv/process.hh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh index f732a4436..2a27f350e 100644 --- a/src/arch/riscv/process.hh +++ b/src/arch/riscv/process.hh @@ -48,17 +48,19 @@ class RiscvProcess : public Process protected: RiscvProcess(ProcessParams * params, ObjectFile *objFile); - void initState(); + void initState() override; template void argsInit(int pageSize); public: - RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i); + RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; /// Explicitly import the otherwise hidden getSyscallArg using Process::getSyscallArg; - void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val); - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); + void setSyscallArg(ThreadContext *tc, int i, + RiscvISA::IntReg val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; virtual bool mmapGrowsDown() const override { return false; } }; -- 2.30.2