From 9aba9521933abc4cd2bc394790f64aa461c0c83b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 13:12:38 +0100 Subject: [PATCH] move fail-on-first to appendix --- simple_v_extension/appendix.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn index 65a573dd4..6e883137c 100644 --- a/simple_v_extension/appendix.mdwn +++ b/simple_v_extension/appendix.mdwn @@ -130,7 +130,7 @@ other sections. Adding in support for SUBVL is a matter of adding in an extra inner for-loop, where register src and dest are still incremented inside the -inner part. Not that the predication is still taken from the VL index. +inner part. Note that the predication is still taken from the VL index. So whilst elements are indexed by "(i * SUBVL + s)", predicate bits are indexed by "(i)" -- 2.30.2