From 9abc54fea430c13e8bcc98c1ed58b540644118a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 10 Apr 2020 13:57:12 +0100 Subject: [PATCH] converting InstructionQ to use Decode2ToExecuteType needed to convert Decode2ToExecuteType to use RecordObject --- src/soc/decoder/power_decoder2.py | 32 ++++++----------------------- src/soc/experiment/alu_hier.py | 4 ++-- src/soc/scoreboard/instruction_q.py | 19 ++++++----------- 3 files changed, 14 insertions(+), 41 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 63da5497..52d98103 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -6,6 +6,8 @@ based on Anton Blanchard microwatt decode2.vhdl from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record from nmigen.cli import rtlil +from nmutil.iocontrol import RecordObject + from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_enums import (InternalOp, CryIn, Function, LdstLen, In1Sel, In2Sel, In3Sel, @@ -283,9 +285,11 @@ class XerBits: return [self.ca, self.ca32, self.ov, self.ov32, self.so, ] -class Decode2ToExecute1Type: +class Decode2ToExecute1Type(RecordObject): - def __init__(self): + def __init__(self, name=None): + + RecordObject.__init__(self, name=name) self.valid = Signal(reset_less=True) self.insn_type = Signal(InternalOp, reset_less=True) @@ -320,30 +324,6 @@ class Decode2ToExecute1Type: self.sign_extend = Signal(reset_less=True)# do we need this? self.update = Signal(reset_less=True) # is this an update instruction? - def ports(self): - return [self.valid, self.insn_type, self.nia, - #self.read_data1, self.read_data2, self.read_data3, - #self.cr, - self.lk, - self.invert_a, self.invert_out, - self.input_carry, self.output_carry, - self.input_cr, self.output_cr, - self.is_32bit, self.is_signed, - self.insn, - self.data_len, self.byte_reverse , self.sign_extend , - self.update] + \ - self.oe.ports() + \ - self.rc.ports() + \ - self.write_spr.ports() + \ - self.read_spr1.ports() + \ - self.read_spr2.ports() + \ - self.write_reg.ports() + \ - self.read_reg1.ports() + \ - self.read_reg2.ports() + \ - self.read_reg3.ports() + \ - self.imm_data.ports() - # + self.xerc.ports() - class PowerDecode2(Elaboratable): diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 01726258..366dbed8 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -27,7 +27,7 @@ class CompALUOpSubset(Record): needed for ALU operations. use with eq_from_execute1 (below) to grab subsets. """ - def __init__(self): + def __init__(self, name=None): layout = (('insn_type', InternalOp), ('nia', 64), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), @@ -47,7 +47,7 @@ class CompALUOpSubset(Record): ('byte_reverse', 1), ('sign_extend', 1)) - Record.__init__(self, Layout(layout)) + Record.__init__(self, Layout(layout), name=name) # grrr. Record does not have kwargs self.insn_type.reset_less = True diff --git a/src/soc/scoreboard/instruction_q.py b/src/soc/scoreboard/instruction_q.py index 65496a6a..fdfdc297 100644 --- a/src/soc/scoreboard/instruction_q.py +++ b/src/soc/scoreboard/instruction_q.py @@ -6,22 +6,15 @@ from nmigen import Module, Signal, Cat, Array, Const, Repl, Elaboratable from nmutil.iocontrol import RecordObject from nmutil.nmoperator import eq, shape, cat +from soc.decoder.power_decoder2 import Decode2ToExecute1Type -class Instruction(RecordObject): - def __init__(self, name, wid, opwid): - RecordObject.__init__(self, name=name) - self.oper_i = Signal(opwid, reset_less=True) - self.opim_i = Signal(1, reset_less=True) # src2 is an immediate - self.imm_i = Signal(wid, reset_less=True) - self.dest_i = Signal(wid, reset_less=True) - self.src1_i = Signal(wid, reset_less=True) - self.src2_i = Signal(wid, reset_less=True) +class Instruction(Decode2ToExecute1Type): @staticmethod - def nq(n_insns, name, wid, opwid): + def _nq(n_insns, name): q = [] for i in range(n_insns): - q.append(Instruction("%s%d" % (name, i), wid, opwid)) + q.append(Instruction("%s%d" % (name, i))) return Array(q) @@ -53,9 +46,9 @@ class InstructionQ(Elaboratable): self.p_add_i = Signal(mqbits) # instructions to add (from data_i) self.p_ready_o = Signal() # instructions were added - self.data_i = Instruction.nq(n_in, "data_i", wid, opwid) + self.data_i = Instruction._nq(n_in, "data_i") - self.data_o = Instruction.nq(n_out, "data_o", wid, opwid) + self.data_o = Instruction._nq(n_out, "data_o") self.n_sub_i = Signal(mqbits) # number of instructions to remove self.n_sub_o = Signal(mqbits) # number of instructions removed -- 2.30.2