From 9abde121103a0b004e9c9fa256951553f9bb4732 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 15:47:42 -0700
Subject: [PATCH] Add $__XILINX_MUXF78 to preserve entire box

---
 techlibs/xilinx/abc_xc7.box | 11 ++++++++---
 techlibs/xilinx/cells_map.v | 16 ++++++++++++----
 techlibs/xilinx/cells_sim.v |  8 ++++++++
 3 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8a48bad4e..a312646f7 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -1,16 +1,21 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
-# F7BMUX slower than F7AMUX
+# Average across F7[AB]MUX
 # Inputs: I0 I1 S0
 # Outputs: O
-F7BMUX 1 1 3 1
-217 223 296
+F7MUX 1 1 3 1
+204 208 286
 
 # Inputs: I0 I1 S0
 # Outputs: O
 MUXF8 2 1 3 1
 104 94 273
 
+# Inputs: I0 I1 I2 I3 S0 S1
+# Outputs: O
+MUXF78 10 1 6 1
+190 193 217 223 296 273
+
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f139dc5d5..9313df7cc 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -226,7 +226,6 @@ module \$__XILINX_SHIFTX (A, B, Y);
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
       wire [4-1:0] T;
-      wire T0, T1;
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
@@ -238,9 +237,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
         end
         else
           assign T[i] = 1'bx;
-      MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_hard_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
@@ -274,3 +271,14 @@ input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
+
+`ifndef _ABC
+module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
+  output O;
+  input I0, I1, I2, I3, S0, S1;
+  wire T0, T1;
+  MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+endmodule
+`endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bf7a0ed44..3163d8446 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -169,6 +169,14 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+`ifdef _ABC
+(* abc_box_id = 10, lib_whitebox *)
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+  assign O = S1 ? (S0 ? I3 : I2)
+                : (S0 ? I1 : I0);
+endmodule
+`endif
+
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
-- 
2.30.2