From 9ac310b528f89044b8e0a8af0b4931c6f50a78cc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 19 Oct 2018 14:44:09 +0100 Subject: [PATCH] redirect through element width, obtain elwidth from CSR reg tables --- riscv/sv.cc | 9 ++++++ riscv/sv_decode.h | 1 + riscv/sv_insn_redirect.cc | 63 +++++++++++++-------------------------- 3 files changed, 30 insertions(+), 43 deletions(-) diff --git a/riscv/sv.cc b/riscv/sv.cc index e8ae90a..f1a302d 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -230,3 +230,12 @@ void sv_insn_t::setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs, READ_REG(rs1()), READ_REG(rs2())); } +uint8_t sv_insn_t::reg_elwidth(reg_t reg, bool intreg) +{ + sv_reg_entry *r = get_regentry(reg, intreg); + if (r->active) { + return r->elwidth; + } + return 0; +} + diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index 88e4347..c1e3854 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -38,6 +38,7 @@ public: prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp), save_branch_addr(0) {} + uint8_t reg_elwidth(reg_t reg, bool intreg); sv_reg_t rvc_addi4spn_imm() { return sv_reg_t(insn_t::rvc_addi4spn_imm()); } sv_reg_t rvc_imm() { return sv_reg_t(insn_t::rvc_imm()); } sv_reg_t rvc_zimm() { return sv_reg_t(insn_t::rvc_zimm()); } diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index d49ef60..c34d291 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -100,24 +100,31 @@ sv_reg_t (sv_proc_t::READ_REG)(uint64_t i) } */ -sv_reg_t sv_proc_t::get_rs1() -{ - return (_insn->p->get_state()->XPR[_insn->rs1()]); -} +#define GET_REG(name) \ + sv_reg_t sv_proc_t::get_##name() \ + { \ + reg_t reg = _insn->name (); \ + uint8_t elwidth = _insn->reg_elwidth(reg, true); \ + uint64_t data = _insn->p->get_state()->XPR[reg]; \ + return sv_reg_t(data, elwidth); \ + } + +GET_REG(rs1) +GET_REG(rs2) +GET_REG(rs3) +GET_REG(rvc_rs1s) +GET_REG(rvc_rs2s) +GET_REG(rvc_rs1) +GET_REG(rvc_rs2) -sv_reg_t sv_proc_t::get_rs2() +freg_t sv_proc_t::get_frs1() { - return (_insn->p->get_state()->XPR[_insn->rs2()]); + return READ_FREG(_insn->rs1()); } -sv_reg_t sv_proc_t::get_rvc_rs1s() +freg_t sv_proc_t::get_frs2() { - fprintf(stderr, "get_rvc_rs1s %ld\n", _insn->rvc_rs1s()); - sv_reg_entry *r = _insn->get_regentry(_insn->_rvc_rs1s(), true); - fprintf(stderr, "active %d vec %d map %ld\n", - r->active, r->isvec, r->regidx); - - return (_insn->p->get_state()->XPR[_insn->rvc_rs1s()]); + return READ_FREG(_insn->rs2()); } sv_reg_t sv_proc_t::get_shamt() @@ -125,26 +132,6 @@ sv_reg_t sv_proc_t::get_shamt() return sv_reg_t(_insn->i_imm() & 0x3F); } -sv_reg_t sv_proc_t::get_rvc_rs2s() -{ - return (_insn->p->get_state()->XPR[_insn->rvc_rs2s()]); -} - -sv_reg_t sv_proc_t::get_rvc_rs1() -{ - return (_insn->p->get_state()->XPR[_insn->rvc_rs1()]); -} - -sv_reg_t sv_proc_t::get_rvc_rs2() -{ - return (_insn->p->get_state()->XPR[_insn->rvc_rs2()]); -} - -sv_reg_t sv_proc_t::get_rs3() -{ - return (_insn->p->get_state()->XPR[_insn->rs3()]); -} - sv_reg_t sv_proc_t::get_rvc_sp() { return (_insn->p->get_state()->XPR[X_SP]); @@ -210,16 +197,6 @@ sv_reg_t (sv_proc_t::zext32)(sv_reg_t v) return sv_reg_t(x); } -freg_t sv_proc_t::get_frs1() -{ - return READ_FREG(_insn->rs1()); -} - -freg_t sv_proc_t::get_frs2() -{ - return READ_FREG(_insn->rs2()); -} - /* sv_reg_t sv_reg_t::make_sv_int64_t (int64_t v) const { -- 2.30.2