From 9ad43b494e471c0f59471ac1ca7fb8d3a5143fb6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Jul 2020 11:47:05 +0100 Subject: [PATCH] add MSR to PowerDecoder2 --- src/soc/decoder/decode2execute1.py | 1 - src/soc/decoder/power_decoder2.py | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index 8141e2f7..cf1c633c 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -65,7 +65,6 @@ class Decode2ToExecute1Type(RecordObject): if asmcode: self.asmcode = Signal(8, reset_less=True) # only for simulator - self.nia = Signal(64, reset_less=True) self.write_reg = Data(5, name="rego") self.write_ea = Data(5, name="ea") # for LD/ST in update mode self.read_reg1 = Data(5, name="reg1") diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index eba6c71d..ee67a209 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -552,6 +552,7 @@ class PowerDecode2(Elaboratable): self.dec = dec self.e = Decode2ToExecute1Type() + self.msr = Signal(64, reset_less=True) # copy of MSR self.valid = Signal() # sync signal def ports(self): @@ -560,7 +561,7 @@ class PowerDecode2(Elaboratable): def elaborate(self, platform): m = Module() comb = m.d.comb - e, op, do = self.e, self.dec.op, self.e.do + e, op, do, msr = self.e, self.dec.op, self.e.do, self.msr # set up submodule decoders m.submodules.dec = self.dec @@ -594,7 +595,6 @@ class PowerDecode2(Elaboratable): comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data) # set up instruction, pick fn unit - comb += e.nia.eq(0) # XXX TODO (or remove? not sure yet) comb += do.insn_type.eq(op.internal_op) # no op: defaults to OP_ILLEGAL comb += do.fn_unit.eq(op.function_unit) -- 2.30.2