From 9ad49cdb5340bcaab0ecc0574ed754af9ba71283 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Fri, 2 Dec 2016 08:24:27 +0000 Subject: [PATCH] S/390: Add vector pack/unpack patterns. gcc/ChangeLog: 2016-12-02 Andreas Krebbel * config/s390/vector.md (vec_halfhalf): New mode iterator. ("vec_pack_trunc_", "vec_pack_ssat_") ("vec_pack_usat_", "vec_unpacks_hi_v16qi") ("vec_unpacks_low_v16qi", "vec_unpacku_hi_v16qi") ("vec_unpacku_low_v16qi", "vec_unpacks_hi_v8hi") ("vec_unpacks_lo_v8hi", "vec_unpacku_hi_v8hi") ("vec_unpacku_lo_v8hi", "vec_unpacks_hi_v4si") ("vec_unpacks_lo_v4si", "vec_unpacku_hi_v4si") ("vec_unpacku_lo_v4si"): New pattern definitions. * config/s390/vx-builtins.md: Move VI_HW_HSD mode iterator to vector.md. From-SVN: r243157 --- gcc/ChangeLog | 14 +++ gcc/config/s390/vector.md | 198 +++++++++++++++++++++++++++++++-- gcc/config/s390/vx-builtins.md | 1 - 3 files changed, 203 insertions(+), 10 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d06661e26c4..d2ecd0f1d9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2016-12-02 Andreas Krebbel + + * config/s390/vector.md (vec_halfhalf): New mode iterator. + ("vec_pack_trunc_", "vec_pack_ssat_") + ("vec_pack_usat_", "vec_unpacks_hi_v16qi") + ("vec_unpacks_low_v16qi", "vec_unpacku_hi_v16qi") + ("vec_unpacku_low_v16qi", "vec_unpacks_hi_v8hi") + ("vec_unpacks_lo_v8hi", "vec_unpacku_hi_v8hi") + ("vec_unpacku_lo_v8hi", "vec_unpacks_hi_v4si") + ("vec_unpacks_lo_v4si", "vec_unpacku_hi_v4si") + ("vec_unpacku_lo_v4si"): New pattern definitions. + * config/s390/vx-builtins.md: Move VI_HW_HSD mode iterator to + vector.md. + 2016-12-02 Andreas Krebbel * config/s390/s390-protos.h (s390_reverse_condition): New diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index bc4f8dadf3d..d446d5f0db3 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -38,7 +38,8 @@ (define_mode_iterator VIT_HW [V16QI V8HI V4SI V2DI V1TI TI]) (define_mode_iterator VI_HW [V16QI V8HI V4SI V2DI]) (define_mode_iterator VI_HW_QHS [V16QI V8HI V4SI]) -(define_mode_iterator VI_HW_HS [V8HI V4SI]) +(define_mode_iterator VI_HW_HSD [V8HI V4SI V2DI]) +(define_mode_iterator VI_HW_HS [V8HI V4SI]) (define_mode_iterator VI_HW_QH [V16QI V8HI]) ; All integer vector modes supported in a vector register + TImode @@ -114,6 +115,13 @@ (V1DF "V2SF") (V2DF "V4SF") (V1TF "V1DF")]) +; Vector with half the element size AND half the number of elements. +(define_mode_attr vec_halfhalf + [(V2HI "V2QI") (V4HI "V4QI") (V8HI "V8QI") + (V2SI "V2HI") (V4SI "V4HI") + (V2DI "V2SI") + (V2DF "V2SF")]) + ; The comparisons not setting CC iterate over the rtx code. (define_code_iterator VFCMP_HW_OP [eq gt ge]) (define_code_attr asm_fcmp_op [(eq "e") (gt "h") (ge "he")]) @@ -1223,6 +1231,185 @@ "vsel\t%v0,%2,%1,%3" [(set_attr "op_type" "VRR")]) +; vec_pack_trunc + +; vpkh, vpkf, vpkg +(define_insn "vec_pack_trunc_" + [(set (match_operand: 0 "register_operand" "=v") + (vec_concat: + (truncate: + (match_operand:VI_HW_HSD 1 "register_operand" "v")) + (truncate: + (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] + "TARGET_VX" + "vpk\t%0,%1,%2" + [(set_attr "op_type" "VRR")]) + +; vpksh, vpksf, vpksg +(define_insn "vec_pack_ssat_" + [(set (match_operand: 0 "register_operand" "=v") + (vec_concat: + (ss_truncate: + (match_operand:VI_HW_HSD 1 "register_operand" "v")) + (ss_truncate: + (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] + "TARGET_VX" + "vpks\t%0,%1,%2" + [(set_attr "op_type" "VRR")]) + +; vpklsh, vpklsf, vpklsg +(define_insn "vec_pack_usat_" + [(set (match_operand: 0 "register_operand" "=v") + (vec_concat: + (us_truncate: + (match_operand:VI_HW_HSD 1 "register_operand" "v")) + (us_truncate: + (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] + "TARGET_VX" + "vpkls\t%0,%1,%2" + [(set_attr "op_type" "VRR")]) + +;; vector unpack v16qi + +; signed + +(define_insn "vec_unpacks_hi_v16qi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (sign_extend:V8HI + (vec_select:V8QI + (match_operand:V16QI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) + (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] + "TARGET_VX" + "vuphb\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacks_low_v16qi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (sign_extend:V8HI + (vec_select:V8QI + (match_operand:V16QI 1 "register_operand" "v") + (parallel [(const_int 8) (const_int 9) (const_int 10)(const_int 11) + (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))))] + "TARGET_VX" + "vuplb\t%0,%1" + [(set_attr "op_type" "VRR")]) + +; unsigned + +(define_insn "vec_unpacku_hi_v16qi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (zero_extend:V8HI + (vec_select:V8QI + (match_operand:V16QI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) + (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] + "TARGET_VX" + "vuplhb\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacku_low_v16qi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (zero_extend:V8HI + (vec_select:V8QI + (match_operand:V16QI 1 "register_operand" "v") + (parallel [(const_int 8) (const_int 9) (const_int 10)(const_int 11) + (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))))] + "TARGET_VX" + "vupllb\t%0,%1" + [(set_attr "op_type" "VRR")]) + +;; vector unpack v8hi + +; signed + +(define_insn "vec_unpacks_hi_v8hi" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (sign_extend:V4SI + (vec_select:V4HI + (match_operand:V8HI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))))] + "TARGET_VX" + "vuphh\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacks_lo_v8hi" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (sign_extend:V4SI + (vec_select:V4HI + (match_operand:V8HI 1 "register_operand" "v") + (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] + "TARGET_VX" + "vuplhw\t%0,%1" + [(set_attr "op_type" "VRR")]) + +; unsigned + +(define_insn "vec_unpacku_hi_v8hi" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (zero_extend:V4SI + (vec_select:V4HI + (match_operand:V8HI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))))] + "TARGET_VX" + "vuplhh\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacku_lo_v8hi" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (zero_extend:V4SI + (vec_select:V4HI + (match_operand:V8HI 1 "register_operand" "v") + (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] + "TARGET_VX" + "vupllh\t%0,%1" + [(set_attr "op_type" "VRR")]) + +;; vector unpack v4si + +; signed + +(define_insn "vec_unpacks_hi_v4si" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (sign_extend:V2DI + (vec_select:V2SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)]))))] + "TARGET_VX" + "vuphf\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacks_lo_v4si" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (sign_extend:V2DI + (vec_select:V2SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(const_int 2)(const_int 3)]))))] + "TARGET_VX" + "vuplf\t%0,%1" + [(set_attr "op_type" "VRR")]) + +; unsigned + +(define_insn "vec_unpacku_hi_v4si" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (zero_extend:V2DI + (vec_select:V2SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(const_int 0)(const_int 1)]))))] + "TARGET_VX" + "vuplhf\t%0,%1" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_unpacku_lo_v4si" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (zero_extend:V2DI + (vec_select:V2SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(const_int 2)(const_int 3)]))))] + "TARGET_VX" + "vupllf\t%0,%1" + [(set_attr "op_type" "VRR")]) ; reduc_smin @@ -1233,15 +1420,8 @@ ; vec_shl vrep + vsl ; vec_shr -; vec_pack_trunc -; vec_pack_ssat -; vec_pack_usat -; vec_pack_sfix_trunc +; vec_pack_sfix_trunc: convert + pack ? ; vec_pack_ufix_trunc -; vec_unpacks_hi -; vec_unpacks_low -; vec_unpacku_hi -; vec_unpacku_low ; vec_unpacks_float_hi ; vec_unpacks_float_lo ; vec_unpacku_float_hi diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 51d022cf5ce..b3818ee6627 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -24,7 +24,6 @@ (define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF]) (define_mode_iterator VI_HW_SD [V4SI V2DI]) (define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF]) -(define_mode_iterator VI_HW_HSD [V8HI V4SI V2DI]) ; The element type of the vector with floating point modes translated ; to int modes of the same size. -- 2.30.2