From 9ae2b06fa5fa86413d6fb20afe5783c93d443af9 Mon Sep 17 00:00:00 2001
From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 16:08:00 -0400
Subject: [PATCH] Remove TAR input, create fixed input for CTR and input for
 other

Other SPR input will be used for CTR, LR, or TAR for op_bcreg
---
 src/soc/branch/main_stage.py            |  2 +-
 src/soc/branch/pipe_data.py             | 18 +++++++-----------
 src/soc/branch/test/test_pipe_caller.py |  3 +--
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index ebfe5c89..7d21be6a 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -73,7 +73,7 @@ class BranchMainStage(PipeModBase):
         with m.Else():
             # Yes, the CTR only counts 32 bits
             ctr = Signal(64, reset_less=True)
-            comb += ctr.eq(self.i.spr - 1)
+            comb += ctr.eq(self.i.ctr - 1)
             comb += self.o.spr.data.eq(ctr)
             comb += self.o.spr.ok.eq(1)
             ctr_eq_zero = Signal(reset_less=True)
diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 6d97102c..710e5e1e 100644
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -19,26 +19,22 @@ class IntegerData:
 class BranchInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
-        # We need both lr and spr for bclr and bcctrl. Bclr can read
-        # from both ctr and lr, and bcctrl can write to both ctr and
-        # lr.
-        self.lr = Signal(64, reset_less=True)  # Link Register
-        self.spr = Signal(64, reset_less=True) # CTR
-        self.cr = Signal(32, reset_less=True)  # Condition Register(s) CR0-7
-        self.cia = Signal(64, reset_less=True) # Current Instruction Address
-        self.tar = Signal(64, reset_less=True) # Target Address Register
+        # For OP_BCREG, this will either be CTR, LR, or TAR
+        self.spr = Signal(64, reset_less=True)
+        self.ctr = Signal(64, reset_less=True)  # CTR
+        self.cr = Signal(32, reset_less=True)   # Condition Register(s) CR0-7
+        self.cia = Signal(64, reset_less=True)  # Current Instruction Address
 
     def __iter__(self):
         yield from super().__iter__()
-        yield self.lr
+        yield self.ctr
         yield self.spr
         yield self.cr
         yield self.cia
-        yield self.tar
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.lr.eq(i.lr), self.spr.eq(i.spr), self.tar.eq(i.tar),
+        return lst + [self.ctr.eq(i.ctr), self.spr.eq(i.spr),
                       self.cr.eq(i.cr), self.cia.eq(i.cia)]
 
 
diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index fdb4edbe..d582e756 100644
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -159,8 +159,7 @@ class TestRunner(FHDLTestCase):
                     yield instruction.eq(ins)          # raw binary instr.
                     yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
                     yield branch.p.data_i.cr.eq(simulator.cr.get_range().value)
-                    yield branch.p.data_i.spr.eq(simulator.spr['CTR'].value)
-                    yield branch.p.data_i.lr.eq(simulator.spr['LR'].value)
+                    yield branch.p.data_i.ctr.eq(simulator.spr['CTR'].value)
                     print(f"cr0: {simulator.crl[0].get_range()}")
                     yield Settle()
                     fn_unit = yield pdecode2.e.fn_unit
-- 
2.30.2