From 9aec7fb4a9fb06a694b629ca63690d92ba32060b Mon Sep 17 00:00:00 2001 From: Steve Ellcey Date: Wed, 10 Mar 2004 00:26:31 +0000 Subject: [PATCH] ia64.md (divsi3): Fix algorithm. * config/ia64/ia64.md (divsi3): Fix algorithm. (udivsi3): Ditto. (setf_exp_xf): Remove '*' from name. * testsuite/gcc.dg/20040309-1.c: New test. From-SVN: r79217 --- gcc/ChangeLog | 7 +++++++ gcc/config/ia64/ia64.md | 20 +++++++++++--------- gcc/testsuite/gcc.dg/20040309-1.c | 17 +++++++++++++++++ 3 files changed, 35 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/20040309-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4593d9f78b2..65b91f7f5a3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2004-03-09 Steve Ellcey + + * config/ia64/ia64.md (divsi3): Fix algorithm. + (udivsi3): Ditto. + (setf_exp_xf): Remove '*' from name. + * testsuite/gcc.dg/20040309-1.c: New test. + 2004-03-09 Ian Lance Taylor * system.h (SUNOS4_SHARED_LIBRARIES): Poison. diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 1c0cc1230e5..c12c8f38764 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -1840,7 +1840,7 @@ (match_operand:SI 2 "general_operand" "")))] "TARGET_INLINE_INT_DIV" { - rtx op1_xf, op2_xf, op0_xf, op0_di, twon34; + rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; REAL_VALUE_TYPE twon34_r; op0_xf = gen_reg_rtx (XFmode); @@ -1857,9 +1857,10 @@ expand_float (op2_xf, operands[2], 0); /* 2^-34 */ - real_2expN (&twon34_r, -34); - twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode); - twon34 = force_reg (XFmode, twon34); + twon34_exp = gen_reg_rtx (DImode); + emit_move_insn (twon34_exp, GEN_INT (65501)); + twon34 = gen_reg_rtx (XFmode); + emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); @@ -1897,7 +1898,7 @@ (match_operand:SI 2 "general_operand" "")))] "TARGET_INLINE_INT_DIV" { - rtx op1_xf, op2_xf, op0_xf, op0_di, twon34; + rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; REAL_VALUE_TYPE twon34_r; op0_xf = gen_reg_rtx (XFmode); @@ -1914,9 +1915,10 @@ expand_float (op2_xf, operands[2], 1); /* 2^-34 */ - real_2expN (&twon34_r, -34); - twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode); - twon34 = force_reg (XFmode, twon34); + twon34_exp = gen_reg_rtx (DImode); + emit_move_insn (twon34_exp, GEN_INT (65501)); + twon34 = gen_reg_rtx (XFmode); + emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); @@ -2712,7 +2714,7 @@ [(set_attr "itanium_class" "fmisc") (set_attr "predicable" "no")]) -(define_insn "*setf_exp_xf" +(define_insn "setf_exp_xf" [(set (match_operand:XF 0 "fr_register_operand" "=f") (unspec:XF [(match_operand:DI 1 "register_operand" "r")] UNSPEC_SETF_EXP))] diff --git a/gcc/testsuite/gcc.dg/20040309-1.c b/gcc/testsuite/gcc.dg/20040309-1.c new file mode 100644 index 00000000000..736150731c7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/20040309-1.c @@ -0,0 +1,17 @@ +/* Test integer mod on ia64. There was a bug in the inline integer + division code. */ + +/* { dg-do run } */ +/* { dg-options "-minline-int-divide-max-throughput" { target ia64-*-* } } */ + +extern void abort (void); + +volatile int i = 10; +volatile int j = 10; + +int main() +{ + int k = i % j; + if (k != 0) abort(); + return 0; +} -- 2.30.2