From 9b046474c95f15338d4c748df9b62871bba6f36f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 26 Jul 2014 00:48:48 +0200 Subject: [PATCH] radeonsi: fix CMASK and HTILE calculations for Hawaii This fixes the checkerboard pattern in glxgears and anything that triggers fast color clear. num_channels is always <= 8, but Hawaii has 16 pipes. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher --- src/gallium/drivers/radeon/r600_texture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 34ecfabfc51..ac9f6808b3e 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -388,7 +388,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, struct r600_cmask_info *out) { unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes; - unsigned num_pipes = rscreen->tiling_info.num_channels; + unsigned num_pipes = rscreen->info.r600_num_tile_pipes; unsigned cl_width, cl_height; switch (num_pipes) { @@ -485,7 +485,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen, { unsigned cl_width, cl_height, width, height; unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; - unsigned num_pipes = rscreen->tiling_info.num_channels; + unsigned num_pipes = rscreen->info.r600_num_tile_pipes; /* HTILE is broken with 1D tiling on old kernels and CIK. */ if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D && -- 2.30.2