From 9b11e9192de3f2daa14c67ec446b3aa068860587 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 6 Feb 2020 10:50:35 +0100 Subject: [PATCH] cpu/vexriscv: update submodule --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 854f9bd2..8baad219 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004 +Subproject commit 8baad219885a47f65959a9cd4870691e84678db4 -- 2.30.2