From 9b17d7bc633ca67231d1ba4c235ddf3afb4f6d15 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Jan 2020 15:46:46 +0000 Subject: [PATCH] reduce linelength <80chars --- src/ieee754/fsgnj/fsgnj.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py index be6060bd..dbdb23d1 100644 --- a/src/ieee754/fsgnj/fsgnj.py +++ b/src/ieee754/fsgnj/fsgnj.py @@ -53,7 +53,7 @@ class FSGNJPipeMod(PipeModBase): # Handle opcodes 0b00 and 0b01, copying or inverting the sign bit of B sign = Mux(opcode[0], ~b1.s, b1.s) - # Handle opcodes 0b10 and 0b11, XORing the sign bits of a and b together. + # Handle opcodes 0b10 and 0b11, XORing sign bits of a and b together. # opcode 0b11 is not defined in the RISCV spec; it is handled # here as equivalent to opcode 0b10 (i.e. a1.s XOR b1.s) # because this requires slightly less logic than making it the -- 2.30.2