From 9b193cbc127cdb55d7f3d352d603d9fdb82c8b63 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 8 Jan 2019 08:51:47 +0000 Subject: [PATCH] add overview to requirements spec --- 3d_gpu/requirements_specification.mdwn | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/3d_gpu/requirements_specification.mdwn b/3d_gpu/requirements_specification.mdwn index 6c0b3e5c5..c4332f82a 100644 --- a/3d_gpu/requirements_specification.mdwn +++ b/3d_gpu/requirements_specification.mdwn @@ -17,8 +17,21 @@ An overview of the design is as follows: * 6600-style scoreboards will be augmented with "shadow" wires and write hazard capability on exceptions, branch speculation, LD/ST and predication. +* Each "shadow" capability will be provided by a separate Function + Unit. If there is to exist the possibility of rolling ahead + through two speculative branches, then two **separate** + Branch-speculative Function Units will be required. +* Likewise for predication, which shall place a "hold" on + the Function Units that depend on it until the register used + as a predicate mask has been read and decoded. +* The 6600 "Q-Table" that records, for each register, the last Function + Unit (in instruction issue order) that is to write its result to that + register, shall be augmented with "history" capability that aids and + assists in "rollback" of "nameless" registers, should an exception + or interrupt occur. * Function Units will have both src and destination Reservation - Stations (latches) in order to buffer incoming and outgoing data + Stations (latches) in order to buffer incoming and outgoing data. + This to make best use of (limited) inter-Function-Unit bus bandwidth. * Crossbar Routing from the Register File will be on the **source** registers **only**: Function Units will route **directly** to and be hard-wired associated with one of four register banks. @@ -30,7 +43,10 @@ An overview of the design is as follows: latches associated with the Function Unit, and will put the result **back** into the destination latch associated with that **same** Function Unit. -* **Pairs** of 32-bit Function Units will handle 64-bit operations. +* **Pairs** of 32-bit Function Units will handle 64-bit operations, + with the 32-bit src Reservation Stations (latches) "teaming up" + to store 64-bit src register values, and likewise the 32-bit + destination latches for the same (paired) Function Units. * 32-bit Function Units will handle 8 and 16 bit operations in cases where batches of operations may be (easily, conveniently) allocated to a 32-bit-wide SIMD-style (predicated) ALU. -- 2.30.2