From 9b2775a8c25bda002eee379453d7e706f34cc082 Mon Sep 17 00:00:00 2001
From: programmerjake <programmerjake@web>
Date: Thu, 27 Jun 2019 23:31:49 +0100
Subject: [PATCH] add originally planned encoding

---
 simple_v_extension/specification/sv.setvl.mdwn | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 5e93d6df8..b9a1730e2 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -58,6 +58,17 @@ notes:
 * the above 4 fit into the "rs2 == x0" case, leaving "rs2 != x0" for
   brownfield encodings.
 
+The encoding I (programmerjake) was planning on using is:
+
+| 31|30   20|19    15|14   12|11 7|6     0| name       |
+|---|-------|--------|-------|----|-------|------------|
+| 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
+| 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
+| 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
+
+It leaves space for future expansion to RV128 and/or multi-register predicates.
+
+
 pseudocode:
 
     regs = [0u64; 128];
-- 
2.30.2