From 9b277fc21ea455a0e0ca9b7acde039e90ddb380d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jan 2019 13:35:52 +0100 Subject: [PATCH] Improve Igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/.gitignore | 4 +-- examples/igloo2/example.fp.pdc | 0 examples/igloo2/example.io.pdc | 0 examples/igloo2/example.sdc | 0 examples/igloo2/example.v | 2 +- examples/igloo2/example.ys | 4 +-- examples/igloo2/libero.tcl | 50 ++++++++++++++++++++++++---------- examples/igloo2/runme.sh | 3 +- 8 files changed, 41 insertions(+), 22 deletions(-) create mode 100644 examples/igloo2/example.fp.pdc create mode 100644 examples/igloo2/example.io.pdc create mode 100644 examples/igloo2/example.sdc diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore index fa3c3d7ed..ea58efc9f 100644 --- a/examples/igloo2/.gitignore +++ b/examples/igloo2/.gitignore @@ -1,3 +1,3 @@ /netlist.edn -/netlist.v -/work +/netlist.vm +/proj diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 3eb7007c5..0e336e557 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,4 +1,4 @@ -module top ( +module example ( input clk, output LED1, output LED2, diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys index 872f97b99..04ea02672 100644 --- a/examples/igloo2/example.ys +++ b/examples/igloo2/example.ys @@ -1,3 +1,3 @@ read_verilog example.v -synth_sf2 -top top -edif netlist.edn -write_verilog netlist.v +synth_sf2 -top example -edif netlist.edn +write_verilog netlist.vm diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 9f6d3b792..b2090f402 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -1,24 +1,38 @@ # Run with "libero SCRIPT:libero.tcl" +file delete -force proj + new_project \ - -name top \ - -location work \ + -name example \ + -location proj \ + -block_mode 1 \ + -hdl "VERILOG" \ -family IGLOO2 \ -die PA4MGL500 \ -package tq144 \ - -speed -1 \ - -hdl VERILOG - -# import_files -edif "[pwd]/netlist.edn" - -import_files -hdl_source "[pwd]/netlist.v" -set_root top - -save_project - -puts "**> SYNTHESIZE" -run_tool -name {SYNTHESIZE} -puts "<** SYNTHESIZE" + -speed -1 + +import_files -hdl_source {netlist.vm} +import_files -sdc {example.sdc} +import_files -io_pdc {example.io.pdc} +import_files -fp_pdc {example.fp.pdc} +set_option -synth 0 + +organize_tool_files -tool PLACEROUTE \ + -file {proj/constraint/example.sdc} \ + -file {proj/constraint/io/example.io.pdc} \ + -file {proj/constraint/fp/example.fp.pdc} \ + -input_type constraint + +organize_tool_files -tool VERIFYTIMING \ + -file {proj/constraint/example.sdc} \ + -input_type constraint + +configure_tool -name PLACEROUTE \ + -params TDPR:true \ + -params PDPR:false \ + -params EFFORT_LEVEL:false \ + -params REPAIR_MIN_DELAY:false puts "**> COMPILE" run_tool -name {COMPILE} @@ -28,6 +42,12 @@ puts "**> PLACEROUTE" run_tool -name {PLACEROUTE} puts "<** PLACEROUTE" +puts "**> VERIFYTIMING" +run_tool -name {VERIFYTIMING} +puts "<** VERIFYTIMING" + +save_project + # puts "**> export_bitstream" # export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} # puts "<** export_bitstream" diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 4edfb5409..54247759f 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,5 +1,4 @@ #!/bin/bash set -ex -rm -rf work -yosys example.ys +yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl -- 2.30.2