From 9b3fad96a672acd1d1b7a4b194065fa8fbb2a547 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Tue, 5 Oct 1993 21:06:46 -0700 Subject: [PATCH] (uns_small_int, uns_arith_operand): New functions. From-SVN: r5626 --- gcc/config/sparc/sparc.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 9f0fb34634f..549fb7e2157 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -434,6 +434,36 @@ small_int (op, mode) return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); } +/* Recognize operand values for the umul instruction. That instruction sign + extends immediate values just like all other sparc instructions, but + interprets the extended result as an unsigned number. */ + +int +uns_small_int (op, mode) + rtx op; + enum machine_mode mode; +{ +#if HOST_BITS_PER_WIDE_INT > 32 + /* All allowed constants will fit a CONST_INT. */ + return (GET_CODE (op) == CONST_INT + && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) + || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L))); +#else + return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) + || (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); +#endif +} + +int +uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return register_operand (op, mode) || uns_small_int (op, mode); +} + /* Return truth value of statement that OP is a call-clobbered register. */ int clobbered_register (op, mode) -- 2.30.2