From 9b458a9aa65eadbe1c3c637d93921d848def9dc1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 13 Jun 2020 08:44:43 +1000 Subject: [PATCH] dmi: Add ASYNC_REG attribute on synchronizers (#200) This tells Vivado to keep them close among other things Signed-off-by: Benjamin Herrenschmidt --- dmi_dtm_xilinx.vhdl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/dmi_dtm_xilinx.vhdl b/dmi_dtm_xilinx.vhdl index 6e47c56..ed92e95 100644 --- a/dmi_dtm_xilinx.vhdl +++ b/dmi_dtm_xilinx.vhdl @@ -127,6 +127,11 @@ architecture behaviour of dmi_dtm is constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00"; constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11"; + attribute ASYNC_REG : string; + attribute ASYNC_REG of jtag_req_0: signal is "TRUE"; + attribute ASYNC_REG of jtag_req_1: signal is "TRUE"; + attribute ASYNC_REG of dmi_ack_0: signal is "TRUE"; + attribute ASYNC_REG of dmi_ack_1: signal is "TRUE"; begin -- Implement the Xilinx bscan2 for series 7 devices (TODO: use PoC to @@ -161,7 +166,6 @@ begin O => jtag_clk ); - -- dmi_req synchronization dmi_req_sync : process(sys_clk) begin -- 2.30.2