From 9b57fd3d96f312194b49fb4774dd2ce075ef5c17 Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Thu, 21 Jun 2018 09:08:43 +0000 Subject: [PATCH] [AArch64][PATCH 2/2] Combine AES instructions with xor and zero operands gcc 2018-06-21 Andre Vieira * config/aarch64/aarch64-simd.md (*aarch64_crypto_aesv16qi_xor_combine): New. gcc/testsuite 2018-06-21 Andre Vieira * gcc/gcc.target/aarch64/aes_xor_combine.c: New test. From-SVN: r261836 --- gcc/ChangeLog | 5 ++ gcc/config/aarch64/aarch64-simd.md | 23 ++++++ gcc/testsuite/ChangeLog | 4 ++ .../gcc.target/aarch64/aes_xor_combine.c | 70 +++++++++++++++++++ 4 files changed, 102 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1731f5a05d2..1e851db45c6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-06-21 Andre Vieira + + * config/aarch64/aarch64-simd.md + (*aarch64_crypto_aesv16qi_xor_combine): New. + 2018-06-21 Andre Vieira * config/aarch64/aarch64-simd.md (aarch64_crypto_aesv16qi): diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7e9ae086b10..315c8dc4b85 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5886,6 +5886,29 @@ [(set_attr "type" "crypto_aese")] ) +(define_insn "*aarch64_crypto_aesv16qi_xor_combine" + [(set (match_operand:V16QI 0 "register_operand" "=w") + (unspec:V16QI [(xor:V16QI + (match_operand:V16QI 1 "register_operand" "%0") + (match_operand:V16QI 2 "register_operand" "w")) + (match_operand:V16QI 3 "aarch64_simd_imm_zero" "")] + CRYPTO_AES))] + "TARGET_SIMD && TARGET_AES" + "aes\\t%0.16b, %2.16b" + [(set_attr "type" "crypto_aese")] +) + +(define_insn "*aarch64_crypto_aesv16qi_xor_combine" + [(set (match_operand:V16QI 0 "register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 3 "aarch64_simd_imm_zero" "") + (xor:V16QI (match_operand:V16QI 1 "register_operand" "%0") + (match_operand:V16QI 2 "register_operand" "w"))] + CRYPTO_AES))] + "TARGET_SIMD && TARGET_AES" + "aes\\t%0.16b, %2.16b" + [(set_attr "type" "crypto_aese")] +) + ;; When AES/AESMC fusion is enabled we want the register allocation to ;; look like: ;; AESE Vn, _ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e58afe59ab3..e32abfaeb0e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-06-21 Andre Vieira + + * gcc/gcc.target/aarch64/aes_xor_combine.c: New test. + 2018-06-21 Andre Vieira * gcc/gcc.target/aarch64/aes_2.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c new file mode 100644 index 00000000000..833e9b3073b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c @@ -0,0 +1,70 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mcpu=cortex-a55+crypto" } */ +#include + +#define AESE(r, v, key) (r = vaeseq_u8 ((v), (key))); +#define AESD(r, v, key) (r = vaesdq_u8 ((v), (key))); + +const uint8x16_t zero = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +uint8x16_t foo0 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESE(dummy, a ^ b, zero); + return dummy; +} + +uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESE(dummy, a ^ b, zero); + AESE(dummy, dummy ^ a, zero); + return dummy; +} + +uint8x16_t bar0 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESE(dummy, zero, a ^ b); + return dummy; +} + +uint8x16_t bar1 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESE(dummy, zero, a ^ b); + AESE(dummy, zero, b ^ dummy); + return dummy; +} + +uint8x16_t foo2 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESD(dummy, a ^ b, zero); + return dummy; +} + +uint8x16_t foo3 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESD(dummy, a ^ b, zero); + AESD(dummy, dummy ^ a, zero); + return dummy; +} + +uint8x16_t bar2 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESD(dummy, zero, a ^ b); + return dummy; +} + +uint8x16_t bar3 (uint8x16_t a, uint8x16_t b) +{ + uint8x16_t dummy; + AESD(dummy, zero, a ^ b); + AESD(dummy, zero, b ^ dummy); + return dummy; +} +/* { dg-final { scan-assembler-not "eor" } } */ +/* { dg-final { scan-assembler-not "mov" } } */ -- 2.30.2