From 9b5b1132778105e699936ed9037e4c817dc224b1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 12:48:51 +0000 Subject: [PATCH] allow selection of alternative FPGAs at commandline --- examples/soc.py | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/examples/soc.py b/examples/soc.py index 8b85648..c688e08 100644 --- a/examples/soc.py +++ b/examples/soc.py @@ -26,10 +26,15 @@ from gram.modules import MT41K256M16 from gram.frontend.wishbone import gramWishbone from nmigen_boards.versa_ecp5 import VersaECP5Platform +from nmigen_boards.ulx3s import ULX3S_85F_Platform +from nmigen_boards.arty_a7 import ArtyA7_100Platform from nmigen_boards.test.blinky import Blinky + from uartbridge import UARTBridge from crg import ECPIX5CRG +import sys + class DDR3SoC(SoC, Elaboratable): def __init__(self, *, @@ -140,14 +145,29 @@ class DDR3SoC(SoC, Elaboratable): if __name__ == "__main__": - platform = VersaECP5Platform() + # create a platform selected from the toolchain. defaults to VERSA_ECP5 + fpga = "versa_ecp5" + if len(sys.argv) == 2: + fpga = sys.argv[1] + platform_kls = {'versa_ecp5': VersaECP5Platform, + 'ulx3s': ULX3S_85F_Platform, + 'arty_a7': ArtyA7_100Platform, + }[fpga] + toolchain = {'arty_a7': "yosys_nextpnr", + 'versa_ecp5': 'Trellis', + 'ulx3s': 'Trellis' + }.get(fpga, None) + platform = platform_kls(toolchain=toolchain) + + # get DDR and UART resource pins ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4}) uart_pins = platform.request("uart", 0) + # set up the SOC soc = DDR3SoC(ddrphy_addr=0xff000000, # DRAM firmware init base dramcore_addr=0x80000000, ddr_addr=0x10000000, @@ -155,4 +175,5 @@ if __name__ == "__main__": uart_pins=uart_pins, fw_addr=None) + # build and upload it platform.build(soc, do_program=True) -- 2.30.2