From 9b6fb97c99abe64147f82a3ea6e6ed598e387482 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 7 Aug 2019 19:15:58 +0000 Subject: [PATCH] [AArch64] Fix INSR for zero floats We used INSR to handle zero integers but not zero floats. 2019-08-07 Richard Sandiford gcc/ * config/aarch64/constraints.md (Z): Handle floating-point zeros too. * config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/init_13.c: New test. From-SVN: r274193 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/constraints.md | 4 ++-- gcc/config/aarch64/predicates.md | 4 ++-- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/aarch64/sve/init_13.c | 17 +++++++++++++++++ 5 files changed, 30 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/init_13.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ef6c201e29f..45050ed2f7b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-07 Richard Sandiford + + * config/aarch64/constraints.md (Z): Handle floating-point zeros too. + * config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise. + 2019-08-07 Richard Sandiford * config/aarch64/aarch64-sve.md (vec_shl_insert_): Add diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 21f9549e660..824000a8423 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -114,8 +114,8 @@ (match_test "aarch64_float_const_zero_rtx_p (op)"))) (define_constraint "Z" - "Integer constant zero." - (match_test "op == const0_rtx")) + "Integer or floating-point constant zero." + (match_test "op == CONST0_RTX (GET_MODE (op))")) (define_constraint "Ush" "A constraint that matches an absolute symbolic address high part." diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 10100ca830a..2cd0b87b287 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -57,9 +57,9 @@ (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) (define_predicate "aarch64_reg_or_zero" - (and (match_code "reg,subreg,const_int") + (and (match_code "reg,subreg,const_int,const_double") (ior (match_operand 0 "register_operand") - (match_test "op == const0_rtx")))) + (match_test "op == CONST0_RTX (GET_MODE (op))")))) (define_predicate "aarch64_reg_or_fp_zero" (ior (match_operand 0 "register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 22cf0e97c12..cf4cbabca69 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-08-07 Richard Sandiford + + * gcc.target/aarch64/sve/init_13.c: New test. + 2019-08-07 Richard Sandiford * gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_13.c b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c new file mode 100644 index 00000000000..eea41706305 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c @@ -0,0 +1,17 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef float vnx4sf __attribute__((vector_size (32))); + +/* +** foo: +** mov (z[0-9]+\.s), s0 +** insr \1, wzr +** ... +*/ +vnx4sf +foo (float a) +{ + return (vnx4sf) { 0.0f, a, a, a, a, a, a, a }; +} -- 2.30.2