From 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Mar 2019 04:17:28 +0000 Subject: [PATCH] get roundz working again, needed for mul stage --- src/add/fmul.py | 3 ++- src/add/fpbase.py | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/add/fmul.py b/src/add/fmul.py index 20ada3ef..8e3ea7d5 100644 --- a/src/add/fmul.py +++ b/src/add/fmul.py @@ -127,7 +127,8 @@ class FPMUL(FPBase): # rounding stage with m.State("round"): - self.roundz(m, z, of, "corrections") + self.roundz(m, z, z, of.roundz) + m.next = "corrections" # ****** # correction stage diff --git a/src/add/fpbase.py b/src/add/fpbase.py index aaf263e8..bd203649 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -561,11 +561,11 @@ class FPBase: def roundz(self, m, z, out_z, roundz): """ performs rounding on the output. TODO: different kinds of rounding """ - m.d.comb += out_z.copy(z) # copies input to output first + #m.d.comb += out_z.copy(z) # copies input to output first with m.If(roundz): - m.d.comb += out_z.m.eq(z.m + 1) # mantissa rounds up + m.d.sync += out_z.m.eq(z.m + 1) # mantissa rounds up with m.If(z.m == z.m1s): # all 1s - m.d.comb += out_z.e.eq(z.e + 1) # exponent rounds up + m.d.sync += out_z.e.eq(z.e + 1) # exponent rounds up def corrections(self, m, z, next_state): """ denormalisation and sign-bug corrections -- 2.30.2