From 9ba83df4c6fa64600337bfe8af9ad4c5fba5785c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 14:13:51 +0000 Subject: [PATCH] add MemoryMap to UART16550 (TODO, put that into UART16550 class) --- examples/{soc.py => ls2.py} | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) rename examples/{soc.py => ls2.py} (93%) diff --git a/examples/soc.py b/examples/ls2.py similarity index 93% rename from examples/soc.py rename to examples/ls2.py index 54ffdd3..09d4043 100644 --- a/examples/soc.py +++ b/examples/ls2.py @@ -7,10 +7,10 @@ # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER # under EU Grants 871528 and 957073, under the LGPLv3+ License -from soc.bus.uart_16550 import UART16550 # opencores 16550 uart from nmigen import (Module, Elaboratable, DomainRenamer) from nmigen.lib.cdc import ResetSynchronizer from nmigen_soc import wishbone, memory +from nmigen_soc.memory import MemoryMap from nmigen_stdio.serial import AsyncSerial from lambdasoc.cpu.minerva import MinervaCPU @@ -19,6 +19,7 @@ from lambdasoc.periph.sram import SRAMPeripheral from lambdasoc.periph.timer import TimerPeripheral from lambdasoc.periph import Peripheral from lambdasoc.soc.base import SoC +from soc.bus.uart_16550 import UART16550 # opencores 16550 uart from gram.core import gramCore from gram.phy.ecp5ddrphy import ECP5DDRPHY @@ -60,8 +61,8 @@ class DDR3SoC(SoC, Elaboratable): # set up clock request generator self.crg = ECPIX5CRG() + # set up CPU, and interrupt interface if False: - # set up CPU, and interrupt interface self.cpu = MinervaCPU(reset_address=0) self._arbiter.add(self.cpu.ibus) # I-Cache Master self._arbiter.add(self.cpu.dbus) # D-Cache Master. TODO JTAG master @@ -82,9 +83,15 @@ class DDR3SoC(SoC, Elaboratable): # UART opencores_16550 = "../../uart16550/rtl/verilog" - pth = __file__ - print (pth) - self.uart = UART16550(verilog_src_dir=opencores_16550) + pth = os.path.split(__file__)[0] + pth = os.path.join(pth, opencores_16550) + fname = os.path.abspath(pth) + print (fname) + self.uart = UART16550(verilog_src_dir=fname) + umap = MemoryMap(addr_width=7, data_width=8, name="uart_map") + #umap.add_resource(self._mem, name="mem", size=1<<5) + self.uart.bus.memory_map = umap + self._decoder.add(self.uart.bus, addr=0xc0002000) # 16550 UART address # DRAM Module -- 2.30.2