From 9bb07246b561e0e17f8491b62e5f88f0c25ce9fb Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 19 Aug 2022 05:16:28 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 95d315411..312b4abb9 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -594,32 +594,6 @@ Swizzle can have a *different SUBVL* is taken into account. Basically Pack/Unpack covers everything that VSX `vpkpx` and other ops can do, and then some: Saturation included, for arithmetic ops. -# No Scalar GPR Move - -Perhaps unsurprisingly the Scalar Power ISA does not have -a Scalar GPR Move instruction: instead, there are a series -of pseudo-op opportunities such as `addi RT,RA,0` or `ori RT,RA,0` -and many more. - -Strictly speaking these may orthogonally be Vectorised and achieve -the same effect as a Vector Move. However these instructions -are marked as `RM-2P-1S1D` and have EXTRA3 Augmentation. In other -words it is not possible to use them in Pack/Unpack Mode. -There is however a trick: [[sv/mv.swizzle]] with a straight linear -mapping (X to X, Y to Y...) -By applying a straight linear swizzle map, the `RM-2P-1S1D-PU` mode -of `sv.mv.swizzle` -is available. - -It has however been decided to make one of the many pseudo-op aliases -a Pack/Unpack variant: `sv.xori RT,RA,0`. This loses half the range -of access of the Scalar regs (r0..r63) due to using an EXTRA2. It was -felt to be better to do this to xori rather than ori or addi. - -Pack/Unpack has to be deployed across SVP64 sparingly (not so uniformly -general) due to the fact that it takes up two RM.EXTRA bits, putting -pressure on developers by restricting the register range as above. - # LD/ST with zero-immediate vs mapreduce mode LD/ST operations with a zero immediate effectively means that on a -- 2.30.2