From 9bb2a7b2fcfeb1ddf5f1ca71a7a4f151ffe3ddb3 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 23 Jun 2020 17:37:26 +0200
Subject: [PATCH] Refactor test code

---
 gram/test/test_common.py                |  1 -
 gram/test/test_compat.py                | 26 ++++++-------------------
 gram/test/{utils/formal.py => utils.py} | 10 +++++++++-
 gram/test/utils/__init__.py             |  0
 4 files changed, 15 insertions(+), 22 deletions(-)
 rename gram/test/{utils/formal.py => utils.py} (90%)
 delete mode 100644 gram/test/utils/__init__.py

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index d1676d4..10e6159 100644
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -1,2 +1 @@
 import unittest
-from .utils.formal import FHDLTestCase
diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
index a1d4b3f..fb1f118 100644
--- a/gram/test/test_compat.py
+++ b/gram/test/test_compat.py
@@ -1,13 +1,11 @@
-import unittest
-from gram.test.utils.formal import FHDLTestCase
-
 from nmigen import *
 from nmigen.hdl.ast import Past
 from nmigen.asserts import Assert, Assume
 
 from gram.compat import *
+from utils import *
 
-class DelayedEnterTestCase(unittest.TestCase):
+class DelayedEnterTestCase(FHDLTestCase):
     def test_sequence(self):
         def sequence(expected_delay):
             m = Module()
@@ -36,11 +34,7 @@ class DelayedEnterTestCase(unittest.TestCase):
 
                 self.assertEqual(delay, expected_delay)
 
-            sim = Simulator(m)
-            with sim.write_vcd("test_compat.vcd"):
-                sim.add_clock(1e-6)
-                sim.add_sync_process(process)
-                sim.run()
+            runSimulation(m, process, "test_delayedenter.vcd")
 
         with self.assertRaises(AssertionError):
             sequence(0)
@@ -50,7 +44,7 @@ class DelayedEnterTestCase(unittest.TestCase):
         sequence(100)
         sequence(1000)
 
-class TimelineTestCase(unittest.TestCase):
+class TimelineTestCase(FHDLTestCase):
     def test_sequence(self):
         sigA = Signal()
         sigB = Signal()
@@ -105,11 +99,7 @@ class TimelineTestCase(unittest.TestCase):
                 self.assertFalse((yield sigA))
                 self.assertFalse((yield sigB))
 
-        sim = Simulator(m)
-        with sim.write_vcd("test_compat.vcd"):
-            sim.add_clock(1e-6)
-            sim.add_sync_process(process)
-            sim.run()
+        runSimulation(m, process, "test_timeline.vcd")
 
 class RoundRobinOutputMatchSpec(Elaboratable):
     def __init__(self, dut):
@@ -148,11 +138,7 @@ class RoundRobinTestCase(FHDLTestCase):
 
             self.assertEqual((yield roundrobin.grant), 0)
 
-        sim = Simulator(m)
-        with sim.write_vcd("test_compat.vcd"):
-            sim.add_clock(1e-6)
-            sim.add_sync_process(process)
-            sim.run()
+        runSimulation(m, process, "test_roundrobin.vcd")
 
     # def test_output_match(self):
     #     roundrobin = RoundRobin(32)
diff --git a/gram/test/utils/formal.py b/gram/test/utils.py
similarity index 90%
rename from gram/test/utils/formal.py
rename to gram/test/utils.py
index cc3b87a..38b8010 100644
--- a/gram/test/utils/formal.py
+++ b/gram/test/utils.py
@@ -8,13 +8,21 @@ import unittest
 import warnings
 from contextlib import contextmanager
 
+from nmigen import *
+from nmigen.back.pysim import *
 from nmigen.hdl.ir import Fragment
 from nmigen.back import rtlil
 from nmigen._toolchain import require_tool
 
 
-__all__ = ["FHDLTestCase"]
+__all__ = ["FHDLTestCase", "runSimulation"]
 
+def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6):
+    sim = Simulator(module)
+    with sim.write_vcd(vcd_filename):
+        sim.add_clock(clock)
+        sim.add_sync_process(process)
+        sim.run()
 
 class FHDLTestCase(unittest.TestCase):
     def assertRepr(self, obj, repr_str):
diff --git a/gram/test/utils/__init__.py b/gram/test/utils/__init__.py
deleted file mode 100644
index e69de29..0000000
-- 
2.30.2