From 9bc71f374a63198ae5010b5f2e5f7aab8ed4c6b9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2015 21:00:12 +0100 Subject: [PATCH] rename sdram mapping to main_ram --- misoclib/soc/__init__.py | 4 ++-- misoclib/soc/sdram.py | 6 +++--- software/bios/boot.c | 14 +++++++------- software/bios/sdram.c | 2 +- software/libbase/system.c | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index 80b26d42..2e2a1f23 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -31,7 +31,7 @@ class SoC(Module): mem_map = { "rom": 0x00000000, # (shadow @0x80000000) "sram": 0x10000000, # (shadow @0x90000000) - "sdram": 0x40000000, # (shadow @0xc0000000) + "main_ram": 0x40000000, # (shadow @0xc0000000) "csr": 0x60000000, # (shadow @0xe0000000) } def __init__(self, platform, clk_freq, cpu_or_bridge=None, @@ -101,7 +101,7 @@ class SoC(Module): # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if with_integrated_main_ram: self.submodules.main_ram = wishbone.SRAM(main_ram_size) - self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size) + self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, main_ram_size) elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU): self._wb_masters += [cpu_or_bridge.wishbone] diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 5ead08d6..5ddf976e 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -63,7 +63,7 @@ class SDRAMSoC(SoC): self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()) lasmic = self.sdram.controller.lasmic main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8 - self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size) + self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size) # MINICON frontend elif self.ramcon_type == "minicon": @@ -71,11 +71,11 @@ class SDRAMSoC(SoC): main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8 if sdram_width == 32: - self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size) + self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size) elif sdram_width < 32: self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width) self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus) - self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size) + self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size) else: raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) diff --git a/software/bios/boot.c b/software/bios/boot.c index 210937e6..b40e6598 100644 --- a/software/bios/boot.c +++ b/software/bios/boot.c @@ -215,12 +215,12 @@ void netboot(void) microudp_start(macadr, IPTOINT(LOCALIP1, LOCALIP2, LOCALIP3, LOCALIP4)); - if(tftp_get_v(ip, "boot.bin", (void *)SDRAM_BASE) <= 0) { + if(tftp_get_v(ip, "boot.bin", (void *)MAIN_RAM_BASE) <= 0) { printf("Network boot failed\n"); return; } - cmdline_adr = SDRAM_BASE+0x1000000; + cmdline_adr = MAIN_RAM_BASE+0x1000000; size = tftp_get_v(ip, "cmdline.txt", (void *)cmdline_adr); if(size <= 0) { printf("No command line parameters found\n"); @@ -228,7 +228,7 @@ void netboot(void) } else *((char *)(cmdline_adr+size)) = 0x00; - initrdstart_adr = SDRAM_BASE+0x1002000; + initrdstart_adr = MAIN_RAM_BASE+0x1002000; size = tftp_get_v(ip, "initrd.bin", (void *)initrdstart_adr); if(size <= 0) { printf("No initial ramdisk found\n"); @@ -237,7 +237,7 @@ void netboot(void) } else initrdend_adr = initrdstart_adr + size; - boot(cmdline_adr, initrdstart_adr, initrdend_adr, SDRAM_BASE); + boot(cmdline_adr, initrdstart_adr, initrdend_adr, MAIN_RAM_BASE); } #endif @@ -260,12 +260,12 @@ void flashboot(void) } printf("Loading %d bytes from flash...\n", length); - memcpy((void *)SDRAM_BASE, flashbase, length); - got_crc = crc32((unsigned char *)SDRAM_BASE, length); + memcpy((void *)MAIN_RAM_BASE, flashbase, length); + got_crc = crc32((unsigned char *)MAIN_RAM_BASE, length); if(crc != got_crc) { printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc); return; } - boot(0, 0, 0, SDRAM_BASE); + boot(0, 0, 0, MAIN_RAM_BASE); } #endif diff --git a/software/bios/sdram.c b/software/bios/sdram.c index 2ca55da6..d374e9d3 100644 --- a/software/bios/sdram.c +++ b/software/bios/sdram.c @@ -429,7 +429,7 @@ int sdrlevel(void) int memtest_silent(void) { - volatile unsigned int *array = (unsigned int *)SDRAM_BASE; + volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE; int i; unsigned int prv; unsigned int error_cnt; diff --git a/software/libbase/system.c b/software/libbase/system.c index ca618504..f0ea28fa 100644 --- a/software/libbase/system.c +++ b/software/libbase/system.c @@ -77,7 +77,7 @@ void flush_l2_cache(void) l2_nwords = 1 << wishbone2lasmi_cachesize_read(); for(i=0;i<2*l2_nwords;i++) { - addr = SDRAM_BASE + i*4; + addr = MAIN_RAM_BASE + i*4; #ifdef __lm32__ __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr)); #else -- 2.30.2