From 9beb3391b5500b17c860356facab9fcff032693b Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 26 Jul 2019 11:30:06 -0700 Subject: [PATCH] pan/midgard: Tag SSA/reg Rather than putting registers after SSA in the MIR indexing, put them side-by-side, shifted 1, using the bottom bit as the SSA/reg select. This will allow us to generate SSA temps in the compiler. Signed-off-by: Alyssa Rosenzweig --- src/panfrost/midgard/compiler.h | 10 ++++++++++ src/panfrost/midgard/helpers.h | 4 ++-- src/panfrost/midgard/midgard_compile.c | 14 ++++++++------ src/panfrost/midgard/midgard_opt_copy_prop.c | 4 ++-- src/panfrost/midgard/midgard_opt_perspective.c | 8 ++++---- src/panfrost/midgard/midgard_schedule.c | 4 +--- src/panfrost/midgard/mir_promote_uniforms.c | 2 +- 7 files changed, 28 insertions(+), 18 deletions(-) diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index 53d995a109e..f0cdc03038b 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -370,6 +370,16 @@ mir_is_alu_bundle(midgard_bundle *bundle) return IS_ALU(bundle->tag); } +/* Registers/SSA are distinguish in the backend by the bottom-most bit */ + +#define IS_REG (1) + +static inline unsigned +make_compiler_temp(compiler_context *ctx) +{ + return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1; +} + /* MIR manipulation */ void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new); diff --git a/src/panfrost/midgard/helpers.h b/src/panfrost/midgard/helpers.h index 92545cfc787..0cd2e71862c 100644 --- a/src/panfrost/midgard/helpers.h +++ b/src/panfrost/midgard/helpers.h @@ -177,8 +177,8 @@ quadword_size(int tag) #define SSA_UNUSED_1 -2 #define SSA_FIXED_SHIFT 24 -#define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT) -#define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1) +#define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1) +#define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1) #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0) /* Swizzle support */ diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 48f7bbd38b5..46f0725741b 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -297,10 +297,10 @@ static unsigned nir_dest_index(compiler_context *ctx, nir_dest *dst) { if (dst->is_ssa) - return dst->ssa.index; + return (dst->ssa.index << 1) | 0; else { assert(!dst->reg.indirect); - return ctx->func->impl->ssa_alloc + dst->reg.reg->index; + return (dst->reg.reg->index << 1) | IS_REG; } } @@ -533,7 +533,9 @@ emit_load_const(compiler_context *ctx, nir_load_const_instr *instr) float *v = rzalloc_array(NULL, float, 4); nir_const_load_to_arr(v, instr, f32); - _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v); + + /* Shifted for SSA, +1 for off-by-one */ + _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, v); } /* Normally constants are embedded implicitly, but for I/O and such we have to @@ -555,10 +557,10 @@ static unsigned nir_src_index(compiler_context *ctx, nir_src *src) { if (src->is_ssa) - return src->ssa->index; + return (src->ssa->index << 1) | 0; else { assert(!src->reg.indirect); - return ctx->func->impl->ssa_alloc + src->reg.reg->index; + return (src->reg.reg->index << 1) | IS_REG; } } @@ -2003,7 +2005,7 @@ midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block) /* TODO: Registers? */ unsigned src = ins->ssa_args.src1; - if (src >= ctx->func->impl->ssa_alloc) continue; + if (src & IS_REG) continue; assert(!mir_has_multiple_writes(ctx, src)); /* There might be a source modifier, too */ diff --git a/src/panfrost/midgard/midgard_opt_copy_prop.c b/src/panfrost/midgard/midgard_opt_copy_prop.c index 32d830d6ac7..c2cf7eb69e3 100644 --- a/src/panfrost/midgard/midgard_opt_copy_prop.c +++ b/src/panfrost/midgard/midgard_opt_copy_prop.c @@ -41,8 +41,8 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block) if (to >= SSA_FIXED_MINIMUM) continue; if (from >= SSA_FIXED_MINIMUM) continue; - if (to >= ctx->func->impl->ssa_alloc) continue; - if (from >= ctx->func->impl->ssa_alloc) continue; + if (to & IS_REG) continue; + if (from & IS_REG) continue; /* Constant propagation is not handled here, either */ if (ins->ssa_args.inline_constant) continue; diff --git a/src/panfrost/midgard/midgard_opt_perspective.c b/src/panfrost/midgard/midgard_opt_perspective.c index df826bc30c1..3ab94deed58 100644 --- a/src/panfrost/midgard/midgard_opt_perspective.c +++ b/src/panfrost/midgard/midgard_opt_perspective.c @@ -64,8 +64,8 @@ midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block) unsigned frcp = ins->ssa_args.src1; unsigned to = ins->ssa_args.dest; - if (frcp >= ctx->func->impl->ssa_alloc) continue; - if (to >= ctx->func->impl->ssa_alloc) continue; + if (frcp & IS_REG) continue; + if (to & IS_REG) continue; bool frcp_found = false; unsigned frcp_component = 0; @@ -150,8 +150,8 @@ midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block) unsigned vary = ins->ssa_args.src0; unsigned to = ins->ssa_args.dest; - if (vary >= ctx->func->impl->ssa_alloc) continue; - if (to >= ctx->func->impl->ssa_alloc) continue; + if (vary & IS_REG) continue; + if (to & IS_REG) continue; if (!mir_single_use(ctx, vary)) continue; /* Check for a varying source. If we find it, we rewrite */ diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index e180a1d860e..62135010d98 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -464,9 +464,7 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction /* All of r0 has to be written out along with * the branch writeout */ - unsigned node_count = ctx->func->impl->ssa_alloc + ctx->func->impl->reg_alloc; - - if (ains->writeout && !can_writeout_fragment(ctx, scheduled, index, node_count)) { + if (ains->writeout && !can_writeout_fragment(ctx, scheduled, index, ctx->temp_count)) { /* We only work on full moves * at the beginning. We could * probably do better */ diff --git a/src/panfrost/midgard/mir_promote_uniforms.c b/src/panfrost/midgard/mir_promote_uniforms.c index b494d3b5b2f..348fa31f3c7 100644 --- a/src/panfrost/midgard/mir_promote_uniforms.c +++ b/src/panfrost/midgard/mir_promote_uniforms.c @@ -72,7 +72,7 @@ midgard_promote_uniforms(compiler_context *ctx, unsigned register_pressure) /* We do need the move for safety for a non-SSA dest, or if * we're being fed into a special class */ - bool needs_move = ins->ssa_args.dest >= ctx->func->impl->ssa_alloc; + bool needs_move = ins->ssa_args.dest & IS_REG; needs_move |= mir_special_index(ctx, ins->ssa_args.dest); if (needs_move) { -- 2.30.2