From 9bee12160bed72dae5cdb006ea38c40f89e174da Mon Sep 17 00:00:00 2001 From: Pierre Moreau Date: Sun, 3 Dec 2017 21:28:57 +0100 Subject: [PATCH] nvc0/ir: Properly lower 64-bit shifts when the shift value is >32 Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30" Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current set-up: uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901 uniform uint64_t uval 0x1400000085010203 uniform int shl 36 uniform int shr 36 uniform int64_t iexpected_shl 0x09ac901000000000 uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010 uniform uint64_t uexpected_shl 0x5010203000000000 uniform uint64_t uexpected_shr 0x0000000001400000 draw rect ortho 12 0 4 4 Signed-off-by: Pierre Moreau Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 7243b1d2e41..6b51b7607cb 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -216,7 +216,7 @@ NVC0LegalizeSSA::handleShift(Instruction *lo) // Compute LO (all shift values) bld.mkOp2(op, type, (dst[0] = bld.getSSA()), src[0], shift); // Compute HI (shift > 32) - bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[1], + bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[0], bld.mkOp1v(OP_NEG, TYPE_S32, bld.getSSA(), x32_minus_shift)) ->setPredicate(CC_NOT_P, pred); bld.mkOp2(OP_UNION, TYPE_U32, (dst[1] = bld.getSSA()), hi1, hi2); -- 2.30.2