From 9bfa69243b8d2d7f9bcef284e3387c81f935ac70 Mon Sep 17 00:00:00 2001 From: klehman Date: Sat, 18 Sep 2021 07:44:01 -0400 Subject: [PATCH] added get_mem --- src/soc/simple/test/teststate.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py index a446d415..3b7eeb20 100644 --- a/src/soc/simple/test/teststate.py +++ b/src/soc/simple/test/teststate.py @@ -49,6 +49,19 @@ class HDLState(State): self.pcl.append(self.pc) log("class hdl pc", hex(self.pc)) + def get_mem(self): + if hasattr(self.core.l0.pimem, 'lsui'): + hdlmem = self.core.l0.pimem.lsui.mem + else: + hdlmem = self.core.l0.pimem.mem + if not isinstance(hdlmem, Memory): + hdlmem = hdlmem.mem + self.mem = [] + for i in range(hdlmem.depth): + value = yield hdlmem._array[i] + if value != 0: # for comparison purposes + self.mem.append(((i*8), value)) + # add to State Factory state_add('hdl', HDLState) -- 2.30.2