From 9c03036a8f1cdb8dcf79a042d5ff9afc219d1dc7 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Fri, 4 Apr 1997 21:07:02 +0000 Subject: [PATCH] * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. * Makefile.in (CFILES): Add them. (ALL_MACHINES): Add them. (dependencies): Regenerate. * configure.in (cgen_files): New variable. (bfd_m32r_arch): Add entry. * configure: Regenerate. --- opcodes/ChangeLog | 11 + opcodes/Makefile.in | 24 ++ opcodes/cgen-asm.c | 276 ++++++++++++ opcodes/cgen-dis.c | 168 ++++++++ opcodes/cgen-opc.c | 312 ++++++++++++++ opcodes/configure | 241 ++++++++--- opcodes/configure.in | 9 +- opcodes/m32r-asm.c | 766 +++++++++++++++++++++++++++++++++ opcodes/m32r-dis.c | 585 ++++++++++++++++++++++++++ opcodes/m32r-opc.c | 977 +++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 3312 insertions(+), 57 deletions(-) create mode 100644 opcodes/cgen-asm.c create mode 100644 opcodes/cgen-dis.c create mode 100644 opcodes/cgen-opc.c create mode 100644 opcodes/m32r-asm.c create mode 100644 opcodes/m32r-dis.c create mode 100644 opcodes/m32r-opc.c diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index df1577929ce..8d3bd4dae20 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +Fri Apr 4 12:29:38 1997 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. + * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. + * Makefile.in (CFILES): Add them. + (ALL_MACHINES): Add them. + (dependencies): Regenerate. + * configure.in (cgen_files): New variable. + (bfd_m32r_arch): Add entry. + * configure: Regenerate. + Fri Apr 4 14:04:16 1997 Ian Lance Taylor * Makefile.in: Rebuild dependencies. diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index d32481bca8e..9404ba67bbe 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -91,6 +91,9 @@ CFILES = \ alpha-dis.c \ alpha-opc.c \ arm-dis.c \ + cgen-asm.c \ + cgen-dis.c \ + cgen-opc.c \ d10v-dis.c \ d10v-opc.c \ dis-buf.c \ @@ -100,6 +103,9 @@ CFILES = \ hppa-dis.c \ i386-dis.c \ i960-dis.c \ + m32r-asm.c \ + m32r-dis.c \ + m32r-opc.c \ m68k-dis.c \ m68k-opc.c \ m88k-dis.c \ @@ -129,6 +135,9 @@ ALL_MACHINES = \ arc-opc.o \ $(end-sanitize-arc) \ arm-dis.o \ + cgen-asm.o \ + cgen-dis.o \ + cgen-opc.o \ d10v-dis.o \ d10v-opc.o \ $(start-sanitize-d30v) \ @@ -140,6 +149,9 @@ ALL_MACHINES = \ hppa-dis.o \ i386-dis.o \ i960-dis.o \ + m32r-asm.o \ + m32r-dis.o \ + m32r-opc.o \ m68k-dis.o \ m68k-opc.o \ m88k-dis.o \ @@ -399,6 +411,12 @@ alpha-opc.o: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \ $(BFD_H) arm-dis.o: arm-dis.c $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ arm-opc.h +cgen-asm.o: cgen-asm.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/opcode/cgen.h +cgen-dis.o: cgen-dis.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/opcode/cgen.h +cgen-opc.o: cgen-opc.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/opcode/cgen.h d10v-dis.o: d10v-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h \ $(INCDIR)/dis-asm.h $(BFD_H) d10v-opc.o: d10v-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h @@ -416,6 +434,12 @@ i386-dis.o: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h sysdep.h config.h i960-dis.o: i960-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h +m32r-asm.o: m32r-asm.c $(INCDIR)/ansidecl.h $(BFD_H) \ + m32r-opc.h $(INCDIR)/opcode/cgen.h +m32r-dis.o: m32r-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h \ + $(BFD_H) m32r-opc.h $(INCDIR)/opcode/cgen.h +m32r-opc.o: m32r-opc.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) m32r-opc.h $(INCDIR)/opcode/cgen.h m68k-dis.o: m68k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h $(INCDIR)/opcode/m68k.h m68k-opc.o: m68k-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68k.h diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c new file mode 100644 index 00000000000..bbc45dac024 --- /dev/null +++ b/opcodes/cgen-asm.c @@ -0,0 +1,276 @@ +/* CGEN generic assembler support code. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STRINGS_H +#include +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "opcode/cgen.h" + +/* This is not published as part of the public interface so we don't + declare this in cgen.h. */ +extern CGEN_OPCODE_DATA *cgen_current_opcode_data; + +/* Assembler instruction hash table. */ +static CGEN_INSN_LIST **asm_hash_table; + +void +cgen_asm_init () +{ + if (asm_hash_table) + { + free (asm_hash_table); + asm_hash_table = NULL; + } +} + +/* Build the assembler instruction hash table. */ + +static void +build_asm_hash_table () +{ + int i; + unsigned int hash; + int count = cgen_insn_count (); + CGEN_OPCODE_DATA *data = cgen_current_opcode_data; + CGEN_INSN_TABLE *insn_table = data->insn_table; + unsigned int hash_size = insn_table->asm_hash_table_size; + const CGEN_INSN *insn; + CGEN_INSN_LIST *insn_lists,*new_insns; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + asm_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *) + + count * sizeof (CGEN_INSN_LIST)); + memset (asm_hash_table, 0, + hash_size * sizeof (CGEN_INSN_LIST *) + + count * sizeof (CGEN_INSN_LIST)); + insn_lists = (CGEN_INSN_LIST *) (asm_hash_table + hash_size); + + /* Add compiled in insns. + The table is scanned backwards as later additions are inserted in + front of earlier ones and we want earlier ones to be prefered. + We stop at the first one as it is a reserved entry. */ + + for (insn = insn_table->init_entries + insn_table->num_init_entries - 1; + insn > insn_table->init_entries; + --insn, ++insn_lists) + { + hash = (*insn_table->asm_hash) (insn->syntax.mnemonic); + insn_lists->next = asm_hash_table[hash]; + insn_lists->insn = insn; + asm_hash_table[hash] = insn_lists; + } + + /* Add runtime added insns. + ??? Currently later added insns will be prefered over earlier ones. + Not sure this is a bug or not. */ + for (new_insns = insn_table->new_entries; + new_insns != NULL; + new_insns = new_insns->next, ++insn_lists) + { + hash = (*insn_table->asm_hash) (new_insns->insn->syntax.mnemonic); + insn_lists->next = asm_hash_table[hash]; + insn_lists->insn = new_insns->insn; + asm_hash_table[hash] = insn_lists; + } +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_asm_lookup_insn (insn) + const char *insn; +{ + unsigned int hash; + + if (asm_hash_table == NULL) + build_asm_hash_table (); + + hash = (*cgen_current_opcode_data->insn_table->asm_hash) (insn); + return asm_hash_table[hash]; +} + +/* Keyword parser. + The result is NULL upon success or an error message. + If successful, *STRP is updated to point passed the keyword. + + ??? At present we have a static notion of how to pick out a keyword. + Later we can allow a target to customize this if necessary [say by + recording something in the keyword table]. */ + +const char * +cgen_parse_keyword (strp, keyword_table, valuep) + const char **strp; + struct cgen_keyword *keyword_table; + long *valuep; +{ + const struct cgen_keyword_entry *ke; + char buf[256]; + const char *p; + + p = *strp; + + /* Allow any first character. */ + if (*p) + ++p; + + /* Now allow letters, digits, and _. */ + while (isalnum (*p) || *p == '_') + ++p; + + if (p - *strp > 255) + return "unrecognized keyword/register name"; + + memcpy (buf, *strp, p - *strp); + buf[p - *strp] = 0; + + ke = cgen_keyword_lookup_name (keyword_table, buf); + + if (ke != NULL) + { + *valuep = ke->value; + *strp = p; + return NULL; + } + + return "unrecognized keyword/register name"; +} + +/* Signed integer parser. */ + +const char * +cgen_parse_signed_integer (strp, opindex, min, max, valuep) + const char **strp; + int opindex; + long min, max; + long *valuep; +{ + long value; + enum cgen_asm_result result; + const char *errmsg; + + errmsg = cgen_asm_parse_operand (strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + { + if (value < min || value > max) + return "integer operand out of range"; + *valuep = value; + } + return errmsg; +} + +/* Unsigned integer parser. */ + +const char * +cgen_parse_unsigned_integer (strp, opindex, min, max, valuep) + const char **strp; + int opindex; + unsigned long min, max; + unsigned long *valuep; +{ + unsigned long value; + enum cgen_asm_result result; + const char *errmsg; + + errmsg = cgen_asm_parse_operand (strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + { + if (value < min || value > max) + return "integer operand out of range"; + *valuep = value; + } + return errmsg; +} + +/* Address parser. */ + +const char * +cgen_parse_address (strp, opindex, opinfo, valuep) + const char **strp; + int opindex; + int opinfo; + long *valuep; +{ + long value; + enum cgen_asm_result result; + const char *errmsg; + + errmsg = cgen_asm_parse_operand (strp, opindex, opinfo, &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + { + *valuep = value; + } + return errmsg; +} + +/* Signed integer validation routine. */ + +const char * +cgen_validate_signed_integer (value, min, max) + long value, min, max; +{ + if (value < min || value > max) + { + const char *err = + "operand out of range (%ld not between %ld and %ld)"; + static char buf[100]; + + sprintf (buf, err, value, min, max); + return buf; + } + + return NULL; +} + +/* Unsigned integer validation routine. + Supplying `min' here may seem unnecessary, but we also want to handle + cases where min != 0 (and max > LONG_MAX). */ + +const char * +cgen_validate_unsigned_integer (value, min, max) + unsigned long value, min, max; +{ + if (value < min || value > max) + { + const char *err = + "operand out of range (%lu not between %lu and %lu)"; + static char buf[100]; + + sprintf (buf, err, value, min, max); + return buf; + } + + return NULL; +} diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c new file mode 100644 index 00000000000..384fe5c311b --- /dev/null +++ b/opcodes/cgen-dis.c @@ -0,0 +1,168 @@ +/* CGEN generic disassembler support code. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STRINGS_H +#include +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "opcode/cgen.h" + +/* This is not published as part of the public interface so we don't + declare this in cgen.h. */ +extern CGEN_OPCODE_DATA *cgen_current_opcode_data; + +/* Disassembler instruction hash table. */ +static CGEN_INSN_LIST **dis_hash_table; + +void +cgen_dis_init () +{ + if (dis_hash_table) + { + free (dis_hash_table); + dis_hash_table = NULL; + } +} + +/* Build the disassembler instruction hash table. */ + +static void +build_dis_hash_table () +{ + int i; + int big_p = cgen_current_endian == CGEN_ENDIAN_BIG; + unsigned int hash; + char buf[4]; + unsigned long value; + int count = cgen_insn_count (); + CGEN_OPCODE_DATA *data = cgen_current_opcode_data; + CGEN_INSN_TABLE *insn_table = data->insn_table; + unsigned int hash_size = insn_table->dis_hash_table_size; + const CGEN_INSN *insn; + CGEN_INSN_LIST *insn_lists,*new_insns; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + dis_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *) + + count * sizeof (CGEN_INSN_LIST *)); + memset (dis_hash_table, 0, + hash_size * sizeof (CGEN_INSN_LIST *) + + count * sizeof (CGEN_INSN_LIST)); + insn_lists = (CGEN_INSN_LIST *) (dis_hash_table + hash_size); + + /* Add compiled in insns. + The table is scanned backwards as later additions are inserted in + front of earlier ones and we want earlier ones to be prefered. + We stop at the first one as it is a reserved entry. */ + + for (insn = insn_table->init_entries + insn_table->num_init_entries - 1; + insn > insn_table->init_entries; + --insn, ++insn_lists) + { + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + value = insn->syntax.value; + switch (CGEN_INSN_BITSIZE (insn)) + { + case 8: + buf[0] = value; + break; + case 16: + if (big_p) + bfd_putb16 ((bfd_vma) value, buf); + else + bfd_putl16 ((bfd_vma) value, buf); + break; + case 32: + if (big_p) + bfd_putb32 ((bfd_vma) value, buf); + else + bfd_putl32 ((bfd_vma) value, buf); + break; + default: + abort (); + } + hash = (*insn_table->dis_hash) (buf, value); + insn_lists->next = dis_hash_table[hash]; + insn_lists->insn = insn; + dis_hash_table[hash] = insn_lists; + } + + /* Add runtime added insns. + ??? Currently later added insns will be prefered over earlier ones. + Not sure this is a bug or not. */ + for (new_insns = insn_table->new_entries; + new_insns != NULL; + new_insns = new_insns->next, ++insn_lists) + { + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + value = new_insns->insn->syntax.value; + switch (CGEN_INSN_BITSIZE (new_insns->insn)) + { + case 8: + buf[0] = value; + break; + case 16: + if (big_p) + bfd_putb16 ((bfd_vma) value, buf); + else + bfd_putl16 ((bfd_vma) value, buf); + break; + case 32: + if (big_p) + bfd_putb32 ((bfd_vma) value, buf); + else + bfd_putl32 ((bfd_vma) value, buf); + break; + default: + abort (); + } + hash = (*insn_table->dis_hash) (buf, value); + insn_lists->next = dis_hash_table[hash]; + insn_lists->insn = new_insns->insn; + dis_hash_table[hash] = insn_lists; + } +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_dis_lookup_insn (buf, value) + const char *buf; + unsigned long value; +{ + unsigned int hash; + + if (dis_hash_table == NULL) + build_dis_hash_table (); + + hash = (*cgen_current_opcode_data->insn_table->dis_hash) (buf, value); + return dis_hash_table[hash]; +} diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c new file mode 100644 index 00000000000..cbe9d5cd46e --- /dev/null +++ b/opcodes/cgen-opc.c @@ -0,0 +1,312 @@ +/* CGEN generic opcode support. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STRINGS_H +#include +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "opcode/cgen.h" + +/* State variables. + These record the state of the currently selected cpu, machine, endian, etc. + They are set by cgen_set_cpu. */ + +/* Current opcode data. */ +CGEN_OPCODE_DATA *cgen_current_opcode_data; + +/* Current machine (a la BFD machine number). */ +int cgen_current_mach; + +/* Current endian. */ +enum cgen_endian cgen_current_endian = CGEN_ENDIAN_UNKNOWN; + +void +cgen_set_cpu (data, mach, endian) + CGEN_OPCODE_DATA *data; + int mach; + enum cgen_endian endian; +{ + cgen_current_opcode_data = data; + cgen_current_mach = mach; + cgen_current_endian = endian; + +#if 0 /* This isn't done here because it would put assembler support in the + disassembler, etc. The caller is required to call these after calling + us. */ + /* Reset the hash tables. */ + cgen_asm_init (); + cgen_dis_init (); +#endif +} + +static unsigned int hash_keyword_name + PARAMS ((const struct cgen_keyword *, const char *)); +static unsigned int hash_keyword_value + PARAMS ((const struct cgen_keyword *, int)); +static void build_keyword_hash_tables + PARAMS ((struct cgen_keyword *)); + +/* Return number of hash table entries to use for N elements. */ +#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) + +/* Look up *NAMEP in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const struct cgen_keyword_entry * +cgen_keyword_lookup_name (kt, name) + struct cgen_keyword *kt; + const char *name; +{ + const struct cgen_keyword_entry *ke; + const char *p,*n; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->name_hash_table[hash_keyword_name (kt, name)]; + + /* We do case insensitive comparisons. + If that ever becomes a problem, add an attribute that denotes + "do case sensitive comparisons". */ + + while (ke != NULL) + { + n = name; + p = ke->name; + + while (*p + && (*p == *n + || (isalpha (*p) && tolower (*p) == tolower (*n)))) + ++n, ++p; + + if (!*p && !*n) + return ke; + + ke = ke->next_name; + } + + return NULL; +} + +/* Look up VALUE in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const struct cgen_keyword_entry * +cgen_keyword_lookup_value (kt, value) + struct cgen_keyword *kt; + int value; +{ + const struct cgen_keyword_entry *ke; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->value_hash_table[hash_keyword_value (kt, value)]; + + while (ke != NULL) + { + if (value == ke->value) + return ke; + ke = ke->next_value; + } + + return NULL; +} + +/* Add an entry to a keyword table. */ + +void +cgen_keyword_add (kt, ke) + struct cgen_keyword *kt; + struct cgen_keyword_entry *ke; +{ + unsigned int hash; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + hash = hash_keyword_name (kt, ke->name); + ke->next_name = kt->name_hash_table[hash]; + kt->name_hash_table[hash] = ke; + + hash = hash_keyword_value (kt, ke->value); + ke->next_value = kt->value_hash_table[hash]; + kt->value_hash_table[hash] = ke; +} + +/* FIXME: Need function to return count of keywords. */ + +/* Initialize a keyword table search. + SPEC is a specification of what to search for. + A value of NULL means to find every keyword. + Currently NULL is the only acceptable value [further specification + deferred]. + The result is an opaque data item used to record the search status. + It is passed to each call to cgen_keyword_search_next. */ + +struct cgen_keyword_search +cgen_keyword_search_init (kt, spec) + struct cgen_keyword *kt; + const char *spec; +{ + struct cgen_keyword_search search; + + /* FIXME: Need to specify format of PARAMS. */ + if (spec != NULL) + abort (); + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + search.table = kt; + search.spec = spec; + search.current_hash = 0; + search.current_entry = NULL; + return search; +} + +/* Return the next keyword specified by SEARCH. + The result is the next entry or NULL if there are no more. */ + +const struct cgen_keyword_entry * +cgen_keyword_search_next (search) + struct cgen_keyword_search *search; +{ + const struct cgen_keyword_entry *ke; + + /* Has search finished? */ + if (search->current_hash == search->table->hash_table_size) + return NULL; + + /* Search in progress? */ + if (search->current_entry != NULL + /* Anything left on this hash chain? */ + && search->current_entry->next_name != NULL) + { + search->current_entry = search->current_entry->next_name; + return search->current_entry; + } + + /* Move to next hash chain [unless we haven't started yet]. */ + if (search->current_entry != NULL) + ++search->current_hash; + + while (search->current_hash < search->table->hash_table_size) + { + search->current_entry = search->table->name_hash_table[search->current_hash]; + if (search->current_entry != NULL) + return search->current_entry; + ++search->current_hash; + } + + return NULL; +} + +/* Return first entry in hash chain for NAME. */ + +static unsigned int +hash_keyword_name (kt, name) + const struct cgen_keyword *kt; + const char *name; +{ + unsigned int hash; + + for (hash = 0; *name; ++name) + hash += *name; + return hash % kt->hash_table_size; +} + +/* Return first entry in hash chain for VALUE. */ + +static unsigned int +hash_keyword_value (kt, value) + const struct cgen_keyword *kt; + int value; +{ + return value % kt->hash_table_size; +} + +/* Build a keyword table's hash tables. + We probably needn't build the value hash table for the assembler when + we're using the disassembler, but we keep things simple. */ + +static void +build_keyword_hash_tables (kt) + struct cgen_keyword *kt; +{ + int i; + /* Use the number of compiled in entries as an estimate for the + typical sized table [not too many added at runtime]. */ + unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); + + kt->hash_table_size = size; + kt->name_hash_table = (struct cgen_keyword_entry **) + xmalloc (size * sizeof (struct cgen_keyword_entry *)); + memset (kt->name_hash_table, 0, size * sizeof (struct cgen_keyword_entry *)); + kt->value_hash_table = (struct cgen_keyword_entry **) + xmalloc (size * sizeof (struct cgen_keyword_entry *)); + memset (kt->value_hash_table, 0, size * sizeof (struct cgen_keyword_entry *)); + + /* The table is scanned backwards as we want keywords appearing earlier to + be prefered over later ones. */ + for (i = kt->num_init_entries - 1; i >= 0; --i) + cgen_keyword_add (kt, &kt->init_entries[i]); +} + +/* Hardware support. */ + +CGEN_HW_ENTRY * +cgen_hw_lookup (name) + const char *name; +{ + CGEN_HW_ENTRY *hw = cgen_current_opcode_data->hw_list; + + while (hw != NULL) + { + if (strcmp (name, hw->name) == 0) + return hw; + hw = hw->next; + } + + return NULL; +} + +/* Instruction support. */ + +/* Return number of instructions. This includes any added at runtime. */ + +int +cgen_insn_count () +{ + int count = cgen_current_opcode_data->insn_table->num_init_entries; + CGEN_INSN_LIST *insn = cgen_current_opcode_data->insn_table->new_entries; + + for ( ; insn != NULL; insn = insn->next) + ++count; + + return count; +} diff --git a/opcodes/configure b/opcodes/configure index 6e844174139..427e1b18204 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -1,7 +1,7 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.10 +# Generated automatically using autoconf version 2.12 # Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # # This configure script is free software; the Free Software Foundation @@ -55,6 +55,8 @@ mandir='${prefix}/man' # Initialize some other variables. subdirs= MFLAGS= MAKEFLAGS= +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 ac_prev= for ac_option @@ -336,7 +338,7 @@ EOF verbose=yes ;; -version | --version | --versio | --versi | --vers) - echo "configure generated by autoconf version 2.10" + echo "configure generated by autoconf version 2.12" exit 0 ;; -with-* | --with-*) @@ -438,11 +440,14 @@ do done # NLS nuisances. -# Only set LANG and LC_ALL to C if already set. -# These must not be set unconditionally because not all systems understand -# e.g. LANG=C (notably SCO). -if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +# Only set these to C if already set. These must not be set unconditionally +# because not all systems understand e.g. LANG=C (notably SCO). +# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'! +# Non-C LC_CTYPE values break the ctype check. if test "${LANG+set}" = set; then LANG=C; export LANG; fi +if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi +if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi # confdefs.h avoids OS command line length limits that DEFS can exceed. rm -rf conftest* confdefs.h @@ -504,6 +509,7 @@ ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. @@ -615,6 +621,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } fi echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:625: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -629,12 +636,13 @@ NONE) esac host=`$ac_config_sub $host_alias` -host_cpu=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` -host_vendor=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` -host_os=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:646: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -646,12 +654,13 @@ NONE) esac target=`$ac_config_sub $target_alias` -target_cpu=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` -target_vendor=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` -target_os=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:664: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -663,9 +672,9 @@ NONE) esac build=`$ac_config_sub $build_alias` -build_cpu=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` -build_vendor=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` -build_os=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$build" 1>&6 test "$host_alias" != "$target_alias" && @@ -717,6 +726,7 @@ fi # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:730: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -745,6 +755,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:759: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -791,7 +802,47 @@ fi test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:807: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:841: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:846: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -800,7 +851,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:804: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:855: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -808,29 +859,34 @@ fi fi echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + if test $ac_cv_prog_gcc = yes; then GCC=yes - if test "${CFLAGS+set}" != set; then - echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -if eval "test \"`echo '$''{'ac_cv_prog_gcc_g'+set}'`\" = set"; then + ac_test_CFLAGS="${CFLAGS+set}" + ac_save_CFLAGS="$CFLAGS" + CFLAGS= + echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:870: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else echo 'void f(){}' > conftest.c if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then - ac_cv_prog_gcc_g=yes + ac_cv_prog_cc_g=yes else - ac_cv_prog_gcc_g=no + ac_cv_prog_cc_g=no fi rm -f conftest* fi -echo "$ac_t""$ac_cv_prog_gcc_g" 1>&6 - if test $ac_cv_prog_gcc_g = yes; then - CFLAGS="-g -O" - else - CFLAGS="-O" - fi +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 + if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" + elif test $ac_cv_prog_cc_g = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-O2" fi else GCC= @@ -850,6 +906,7 @@ fi # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:910: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -880,6 +937,7 @@ fi # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:941: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -910,6 +968,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:972: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -951,11 +1010,12 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:1014: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS="${IFS}:" for ac_dir in $PATH; do # Account for people who put trailing slashes in PATH elements. case "$ac_dir/" in @@ -978,7 +1038,7 @@ else ;; esac done - IFS="$ac_save_ifs" + IFS="$ac_save_IFS" fi if test "${ac_cv_path_install+set}" = set; then @@ -1032,6 +1092,7 @@ fi echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 +echo "configure:1096: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -1046,33 +1107,37 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1056: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1117: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : else echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1071: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1134: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : else echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 rm -rf conftest* CPP=/lib/cpp fi @@ -1087,26 +1152,29 @@ else fi echo "$ac_t""$CPP" 1>&6 -for ac_hdr in string.h strings.h +for ac_hdr in string.h strings.h stdlib.h do -ac_safe=`echo "$ac_hdr" | tr './\055' '___'` +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:1160: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1104: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1170: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* eval "ac_cv_header_$ac_safe=yes" else echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 rm -rf conftest* eval "ac_cv_header_$ac_safe=no" fi @@ -1114,7 +1182,7 @@ rm -f conftest* fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 - ac_tr_hdr=HAVE_`echo $ac_hdr | tr 'abcdefghijklmnopqrstuvwxyz./\055' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ___'` + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` cat >> confdefs.h < confcache <<\EOF # --recheck option to rerun configure. # EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. (set) 2>&1 | - sed -n "s/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=\${\1='\2'}/p" \ - >> confcache + case `(ac_space=' '; set) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache if cmp -s $cache_file confcache; then : else @@ -1320,7 +1405,7 @@ do echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; -version | --version | --versio | --versi | --vers | --ver | --ve | --v) - echo "$CONFIG_STATUS generated by autoconf version 2.10" + echo "$CONFIG_STATUS generated by autoconf version 2.12" exit 0 ;; -help | --help | --hel | --he | --h) echo "\$ac_cs_usage"; exit 0 ;; @@ -1398,20 +1483,56 @@ s%@BFD_MACHINES@%$BFD_MACHINES%g CEOF EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then - # Support "outfile[:infile]", defaulting infile="outfile.in". + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". case "$ac_file" in - *:*) ac_file_in=`echo "$ac_file"|sed 's%.*:%%'` + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; *) ac_file_in="${ac_file}.in" ;; esac - # Adjust relative srcdir, etc. for subdirectories. + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. # Remove last slash and all that follows it. Not all systems have dirname. ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` @@ -1439,6 +1560,7 @@ for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then [/$]*) INSTALL="$ac_given_INSTALL" ;; *) INSTALL="$ac_dots$ac_given_INSTALL" ;; esac + echo creating "$ac_file" rm -f "$ac_file" configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." @@ -1447,14 +1569,16 @@ for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then # $configure_input" ;; *) ac_comsub= ;; esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` sed -e "$ac_comsub s%@configure_input@%$configure_input%g s%@srcdir@%$srcdir%g s%@top_srcdir@%$top_srcdir%g s%@INSTALL@%$INSTALL%g -" -f conftest.subs $ac_given_srcdir/$ac_file_in > $ac_file +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file fi; done -rm -f conftest.subs +rm -f conftest.s* # These sed commands are passed to sed as "A NAME B NAME C VALUE D", where # NAME is the cpp macro being defined and VALUE is the value it is being given. @@ -1475,11 +1599,17 @@ ac_eB='$%\1#\2define\3' ac_eC=' ' ac_eD='%g' -CONFIG_HEADERS=${CONFIG_HEADERS-"config.h:config.in"} +if test "${CONFIG_HEADERS+set}" != set; then +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +fi for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then - # Support "outfile[:infile]", defaulting infile="outfile.in". + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". case "$ac_file" in - *:*) ac_file_in=`echo "$ac_file"|sed 's%.*:%%'` + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; *) ac_file_in="${ac_file}.in" ;; esac @@ -1487,7 +1617,8 @@ for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then echo creating $ac_file rm -f conftest.frag conftest.in conftest.out - cp $ac_given_srcdir/$ac_file_in conftest.in + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + cat $ac_file_inputs > conftest.in EOF @@ -1515,8 +1646,6 @@ EOF # Break up conftest.vals because some shells have a limit on # the size of here documents, and old seds have small limits too. -# Maximum number of lines to put in a single here document. -ac_max_here_lines=12 rm -f conftest.tail while : @@ -1558,7 +1687,11 @@ cat >> $CONFIG_STATUS <<\EOF fi fi; done +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF case x$CONFIG_HEADERS in xconfig.h:config.in) echo > stamp-h ;; esac exit 0 EOF diff --git a/opcodes/configure.in b/opcodes/configure.in index 9785ba22c06..678010e9f7d 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -113,7 +113,7 @@ AC_SUBST(BFD_PICLIST) AC_SUBST(SHLINK) AC_SUBST(INSTALL_SHLIB) -AC_CHECK_HEADERS(string.h strings.h) +AC_CHECK_HEADERS(string.h strings.h stdlib.h) # target-specific stuff: @@ -143,6 +143,10 @@ do fi done +# Utility var, documents generic cgen support files. + +cgen_files="cgen-opc.o cgen-asm.o cgen-dis.o" + # We don't do any links based on the target system, just makefile config. if test x${all_targets} = xfalse ; then @@ -163,9 +167,7 @@ if test x${all_targets} = xfalse ; then # end-sanitize-arc bfd_arm_arch) ta="$ta arm-dis.o" ;; bfd_convex_arch) ;; -# start-sanitize-d10v bfd_d10v_arch) ta="$ta d10v-dis.o d10v-opc.o" ;; -# end-sanitize-d10v # start-sanitize-d30v bfd_d30v_arch) ta="$ta d30v-dis.o d30v-opc.o" ;; # end-sanitize-d30v @@ -175,6 +177,7 @@ if test x${all_targets} = xfalse ; then bfd_i386_arch) ta="$ta i386-dis.o" ;; bfd_i860_arch) ;; bfd_i960_arch) ta="$ta i960-dis.o" ;; + bfd_m32r_arch) ta="$ta $cgen_files m32r-opc.o m32r-asm.o m32r-dis.o" ;; bfd_m68k_arch) ta="$ta m68k-dis.o m68k-opc.o" ;; bfd_m88k_arch) ta="$ta m88k-dis.o" ;; bfd_mips_arch) ta="$ta mips-dis.o mips-opc.o mips16-opc.o" ;; diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c new file mode 100644 index 00000000000..068b30f3520 --- /dev/null +++ b/opcodes/m32r-asm.c @@ -0,0 +1,766 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +This file is used to generate m32r-asm.c. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "m32r-opc.h" + +/* ??? The layout of this stuff is still work in progress. + For speed in assembly/disassembly, we use inline functions. That of course + will only work for GCC. When this stuff is finished, we can decide whether + to keep the inline functions (and only get the performance increase when + compiled with GCC), or switch to macros, or use something else. +*/ + +static const char *parse_insn_normal + PARAMS ((const struct cgen_insn *, const char **, struct cgen_fields *)); +static void insert_insn_normal + PARAMS ((const struct cgen_insn *, struct cgen_fields *, cgen_insn_t *)); + +/* Default insertion routine. + + SHIFT is negative for left shifts, positive for right shifts. + All bits of VALUE to be inserted must be valid as we don't handle + signed vs unsigned shifts. + + ATTRS is a mask of the boolean attributes. We don't need any at the + moment, but for consistency with extract_normal we have them. */ + +/* FIXME: This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* FIXME: For architectures where insns can be representable as ints, + store insn in `field' struct and add registers, etc. while parsing. */ + +static CGEN_INLINE void +insert_normal (value, attrs, start, length, shift, total_length, buffer) + long value; + unsigned int attrs; + int start, length, shift, total_length; + char *buffer; +{ + bfd_vma x; + +#if 0 /*def CGEN_INT_INSN*/ + *buffer |= ((value & ((1 << length) - 1)) + << (total_length - (start + length))); +#else + switch (total_length) + { + case 8: + x = *(unsigned char *) buffer; + break; + case 16: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + x = bfd_getb16 (buffer); + else + x = bfd_getl16 (buffer); + break; + case 32: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + x = bfd_getb32 (buffer); + else + x = bfd_getl32 (buffer); + break; + default : + abort (); + } + + if (shift < 0) + value <<= -shift; + else + value >>= shift; + + x |= ((value & ((1 << length) - 1)) + << (total_length - (start + length))); + + switch (total_length) + { + case 8: + *buffer = value; + break; + case 16: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb16 (x, buffer); + else + bfd_putl16 (x, buffer); + break; + case 32: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb32 (x, buffer); + else + bfd_putl32 (x, buffer); + break; + default : + abort (); + } +#endif +} + +/* -- assembler routines inserted here */ +/* -- asm.c */ + +/* Handle shigh(), high(). */ + +static const char * +parse_h_hi16 (strp, opindex, min, max, valuep) + const char **strp; + int opindex; + unsigned long min, max; + unsigned long *valuep; +{ + const char *errmsg; + + /* FIXME: Need # in assembler syntax (means '#' is optional). */ + if (**strp == '#') + ++*strp; + + if (strncmp (*strp, "high(", 5) == 0) + { + *strp += 5; + /* FIXME: If value was a number, right shift by 16. */ + errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO, valuep); + if (**strp != ')') + return "missing `)'"; + ++*strp; + return errmsg; + } + else if (strncmp (*strp, "shigh(", 6) == 0) + { + *strp += 6; + /* FIXME: If value was a number, right shift by 16 (+ sign test). */ + errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO, valuep); + if (**strp != ')') + return "missing `)'"; + ++*strp; + return errmsg; + } + + return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); +} + +/* Handle low() in a signed context. Also handle sda(). + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_h_slo16 (strp, opindex, min, max, valuep) + const char **strp; + int opindex; + long min, max; + long *valuep; +{ + const char *errmsg; + + /* FIXME: Need # in assembler syntax (means '#' is optional). */ + if (**strp == '#') + ++*strp; + + if (strncmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep); + if (**strp != ')') + return "missing `)'"; + ++*strp; + return errmsg; + } + + if (strncmp (*strp, "sda(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, valuep); + if (**strp != ')') + return "missing `)'"; + ++*strp; + return errmsg; + } + + return cgen_parse_signed_integer (strp, opindex, min, max, valuep); +} + +/* Handle low() in an unsigned context. + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_h_ulo16 (strp, opindex, min, max, valuep) + const char **strp; + int opindex; + unsigned long min, max; + unsigned long *valuep; +{ + const char *errmsg; + + /* FIXME: Need # in assembler syntax (means '#' is optional). */ + if (**strp == '#') + ++*strp; + + if (strncmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep); + if (**strp != ')') + return "missing `)'"; + ++*strp; + return errmsg; + } + + return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); +} + +/* -- */ + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. +*/ + +CGEN_INLINE const char * +m32r_cgen_parse_operand (opindex, strp, fields) + int opindex; + const char **strp; + struct cgen_fields *fields; +{ + const char *errmsg; + + switch (opindex) + { + case 0 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2); + break; + case 1 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1); + break; + case 2 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1); + break; + case 3 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2); + break; + case 4 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2); + break; + case 5 : + errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1); + break; + case 6 : + errmsg = cgen_parse_signed_integer (strp, 6, -128, 127, &fields->f_simm8); + break; + case 7 : + errmsg = cgen_parse_signed_integer (strp, 7, -32768, 32767, &fields->f_simm16); + break; + case 8 : + errmsg = cgen_parse_unsigned_integer (strp, 8, 0, 15, &fields->f_uimm4); + break; + case 9 : + errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 31, &fields->f_uimm5); + break; + case 10 : + errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 65535, &fields->f_uimm16); + break; + case 11 : + errmsg = parse_h_hi16 (strp, 11, 0, 65535, &fields->f_hi16); + break; + case 12 : + errmsg = parse_h_slo16 (strp, 12, -32768, 32767, &fields->f_simm16); + break; + case 13 : + errmsg = parse_h_ulo16 (strp, 13, 0, 65535, &fields->f_uimm16); + break; + case 14 : + errmsg = cgen_parse_address (strp, 14, 0, &fields->f_uimm24); + break; + case 15 : + errmsg = cgen_parse_address (strp, 15, 0, &fields->f_disp8); + break; + case 16 : + errmsg = cgen_parse_address (strp, 16, 0, &fields->f_disp16); + break; + case 17 : + errmsg = cgen_parse_address (strp, 17, 0, &fields->f_disp24); + break; + + default : + fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex); + abort (); + } + + return errmsg; +} + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. +*/ + +CGEN_INLINE void +m32r_cgen_insert_operand (opindex, fields, buffer) + int opindex; + struct cgen_fields *fields; + cgen_insn_t *buffer; +{ + switch (opindex) + { + case 0 : + insert_normal (fields->f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + break; + case 7 : + insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + break; + case 8 : + insert_normal (fields->f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_hi16, 0|(1<f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + break; + case 13 : + insert_normal (fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp16, 0|(1<f_disp24, 0|(1<f_simm8, -128, 127); + break; + case 7 : + errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); + break; + case 8 : + errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15); + break; + case 9 : + errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31); + break; + case 10 : + errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); + break; + case 11 : + errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535); + break; + case 12 : + errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); + break; + case 13 : + errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); + break; + case 14 : + /* nothing to do */ + break; + case 15 : + /* nothing to do */ + break; + case 16 : + /* nothing to do */ + break; + case 17 : + /* nothing to do */ + break; + + default : + fprintf (stderr, "Unrecognized field %d while validating operand.\n", + opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn *m32r_cgen_parse_handlers[] = { + 0, /* default */ + parse_insn_normal, +}; + +cgen_insert_fn *m32r_cgen_insert_handlers[] = { + 0, /* default */ + insert_insn_normal, +}; + +void +m32r_cgen_init_asm (mach, endian) + int mach; + enum cgen_endian endian; +{ + m32r_cgen_init_tables (mach); + cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian); + cgen_asm_init (); +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. +*/ + +static const char * +parse_insn_normal (insn, strp, fields) + const struct cgen_insn *insn; + const char **strp; + struct cgen_fields *fields; +{ + const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const unsigned char *syn; +#ifdef CGEN_MNEMONIC_OPERANDS + int past_opcode_p; +#endif + + /* If mnemonics are constant, they're not stored with the syntax string. */ +#ifndef CGEN_MNEMONIC_OPERANDS + { + const char *p = syntax->mnemonic; + + while (*p && *p == *str) + ++p, ++str; + if (*p || (*str && !isspace (*str))) + return "unrecognized instruction"; + + while (isspace (*str)) + ++str; + } +#endif + + CGEN_INIT_PARSE (); + cgen_asm_init_parse (); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + for (syn = syntax->syntax; *syn != '\0'; ) + { + /* Non operand chars must match exactly. */ + /* FIXME: Need to better handle whitespace. */ + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + if (*str == CGEN_SYNTAX_CHAR (*syn)) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (*syn == ' ') + past_opcode_p = 1; +#endif + ++syn; + ++str; + } + else + { + /* Syntax char didn't match. Can't be this insn. */ + /* FIXME: would like to return "expected char `c'" */ + return "syntax error"; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = m32r_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (*syn == '\0') + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (isspace (*str)) + ++str; + + if (*str != '\0') + return "junk at end of line"; /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return "unrecognized instruction"; +} + +/* Default insn builder (insert handler). + The instruction is recorded in target byte order. */ + +static void +insert_insn_normal (insn, fields, buffer) + const struct cgen_insn *insn; + struct cgen_fields *fields; + cgen_insn_t *buffer; +{ + const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + bfd_vma value; + const unsigned char *syn; + + CGEN_INIT_INSERT (); + value = syntax->value; + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#if 0 /*def CGEN_INT_INSN*/ + *buffer = value; +#else + switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields))) + { + case 8: + *buffer = value; + break; + case 16: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb16 (value, (char *) buffer); + else + bfd_putl16 (value, (char *) buffer); + break; + case 32: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb32 (value, (char *) buffer); + else + bfd_putl32 (value, (char *) buffer); + break; + default: + abort (); + } +#endif + + /* ??? Rather than scanning the syntax string again, we could store + in `fields' a null terminated list of the fields that are present. */ + + for (syn = syntax->syntax; *syn != '\0'; ++syn) + { + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer); + } +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). */ + +const struct cgen_insn * +m32r_cgen_assemble_insn (str, fields, buf) + const char *str; + struct cgen_fields *fields; + cgen_insn_t *buf; +{ + const char *start; + CGEN_INSN_LIST *ilist; + + /* Skip leading white space. */ + while (isspace (*str)) + ++str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (str); + + /* Keep looking until we find a match. */ + + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const struct cgen_insn *insn = ilist->insn; + +#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ + /* Is this insn supported by the selected cpu? */ + if (! m32r_cgen_insn_supported (insn)) + continue; +#endif + +#if 1 /* FIXME: wip */ + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) + continue; +#endif + + str = start; + + /* Record a default length for the insn. This will get set to the + correct value while parsing. */ + /* FIXME: wip */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + /* ??? The extent to which moving the parse and insert handlers into + this function (thus removing the function call) will speed things up + is unclear. The simplicity and flexibility of the current scheme is + appropriate for now. One could have the best of both worlds with + inline functions but of course that would only work for gcc. Since + we're machine generating some code we could do that here too. Maybe + later. */ + if (! (*CGEN_PARSE_FN (insn)) (insn, &str, fields)) + { + (*CGEN_INSERT_FN (insn)) (insn, fields, buf); + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + /* Try the next entry. */ + } + + /* FIXME: Define this as a callback, or pass back string? */ + as_bad ("bad instruction `%s'", start); + return NULL; +} + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +m32r_cgen_asm_hash_keywords (opvals) + struct cgen_keyword *opvals; +{ + struct cgen_keyword_search search = cgen_keyword_search_init (opvals, NULL); + const struct cgen_keyword_entry *ke; + + while ((ke = cgen_keyword_search_next (&search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! m32r_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (ke->name, ke->value); + } +} diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c new file mode 100644 index 00000000000..7f290195346 --- /dev/null +++ b/opcodes/m32r-dis.c @@ -0,0 +1,585 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +This file is used to generate m32r-dis.c. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "m32r-opc.h" +#include "bfd.h" + +/* ??? The layout of this stuff is still work in progress. + For speed in assembly/disassembly, we use inline functions. That of course + will only work for GCC. When this stuff is finished, we can decide whether + to keep the inline functions (and only get the performance increase when + compiled with GCC), or switch to macros, or use something else. +*/ + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG "*unknown*" + +/* FIXME: Machine generate. */ +#ifndef CGEN_PCREL_OFFSET +#define CGEN_PCREL_OFFSET 0 +#endif + +static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int)); + +static int extract_insn_normal + PARAMS ((const struct cgen_insn *, void *, cgen_insn_t, struct cgen_fields *)); +static void print_insn_normal + PARAMS ((void *, const struct cgen_insn *, struct cgen_fields *, bfd_vma, int)); + +/* Default extraction routine. + + ATTRS is a mask of the boolean attributes. We only need `unsigned', + but for generality we take a bitmask of all of them. */ + +static int +extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep) + void *buf_ctrl; + cgen_insn_t insn_value; + unsigned int attrs; + int start, length, shift, total_length; + long *valuep; +{ + long value; + +#ifdef CGEN_INT_INSN +#if 0 + value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length))) + & ((1 << length) - 1)); +#else + value = ((insn_value >> (total_length - (start + length))) + & ((1 << length) - 1)); +#endif + if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) + && (value & (1 << (length - 1)))) + value -= 1 << length; +#else + /* FIXME: unfinished */ +#endif + + /* This is backwards as we undo the effects of insert_normal. */ + if (shift < 0) + value >>= -shift; + else + value <<= shift; + + *valuep = value; + return 1; +} + +/* Default print handler. */ + +static void +print_normal (dis_info, value, attrs, pc, length) + void *dis_info; + long value; + unsigned int attrs; + unsigned long pc; /* FIXME: should be bfd_vma */ + int length; +{ + disassemble_info *info = dis_info; + + /* Print the operand as directed by the attributes. */ + if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE)) + ; /* nothing to do (??? at least not yet) */ + else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info); + /* ??? Not all cases of this are currently caught. */ + else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR)) + /* FIXME: Why & 0xffffffff? */ + (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); + else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "%ld", value); +} + +/* Keyword print handler. */ + +static void +print_keyword (dis_info, keyword_table, value, attrs) + void *dis_info; + struct cgen_keyword *keyword_table; + long value; + CGEN_ATTR *attrs; +{ + disassemble_info *info = dis_info; + const struct cgen_keyword_entry *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* -- disassembler routines inserted here */ +/* -- dis.c */ + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN my_print_insn + +static int +my_print_insn (pc, info, buf, buflen) + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + unsigned long insn_value; + + /* 32 bit insn? */ + if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) + return print_insn (pc, info, buf, buflen); + + /* Print the first insn. */ + if ((pc & 3) == 0) + { + if (print_insn (pc, info, buf, 16) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + buf += 2; + } + + if (buf[0] & 0x80) + { + /* Parallel. */ + (*info->fprintf_func) (info->stream, " || "); + buf[0] &= 0x7f; + } + else + (*info->fprintf_func) (info->stream, " -> "); + + /* The "& 3" is to ensure the branch address is computed correctly + [if it is a branch]. */ + if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + + return (pc & 3) ? 2 : 4; +} + +/* -- */ + +/* Main entry point for operand extraction. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +CGEN_INLINE int +m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) + int opindex; + void *buf_ctrl; + cgen_insn_t insn_value; + struct cgen_fields *fields; +{ + int length; + + switch (opindex) + { + case 0 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case 1 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case 2 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case 3 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case 4 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case 5 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case 6 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8); + break; + case 7 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); + break; + case 8 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm4); + break; + case 9 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm5); + break; + case 10 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + break; + case 11 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_hi16); + break; + case 12 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); + break; + case 13 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + break; + case 14 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); + break; + case 15 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8); + break; + case 16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16); + break; + case 17 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24); + break; + + default : + fprintf (stderr, "Unrecognized field %d while decoding insn.\n", + opindex); + abort (); + } + + return length; +} + +/* Main entry point for printing operands. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +CGEN_INLINE void +m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length) + int opindex; + disassemble_info *info; + struct cgen_fields *fields; + int attrs; + bfd_vma pc; + int length; +{ + switch (opindex) + { + case 0 : + print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_simm8, 0, pc, length); + break; + case 7 : + print_normal (info, fields->f_simm16, 0, pc, length); + break; + case 8 : + print_normal (info, fields->f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_hi16, 0|(1<f_simm16, 0, pc, length); + break; + case 13 : + print_normal (info, fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp16, 0|(1<f_disp24, 0|(1<syntax; *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn), + buf_ctrl, insn_value, fields); + if (length == 0) + return 0; + } + + /* We recognized and successfully extracted this insn. + If a length is recorded with this insn, it has a fixed length. + Otherwise we require the syntax string to have a fake operand which + sets the `length' field in `flds'. */ + /* FIXME: wip */ + if (syntax->length > 0) + return syntax->length; + return fields->length; +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. +*/ + +static void +print_insn_normal (dis_info, insn, fields, pc, length) + void *dis_info; + const struct cgen_insn *insn; + struct cgen_fields *fields; + bfd_vma pc; + int length; +{ + const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = dis_info; + const unsigned char *syn; + + CGEN_INIT_PRINT (); + + for (syn = syntax->syntax; *syn; ++syn) + { + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Default value for CGEN_PRINT_INSN. + Given BUFLEN bytes (target byte order) read into BUF, look up the + insn in the instruction table and disassemble it. + + The result is the size of the insn in bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN print_insn +#endif + +static int +print_insn (pc, info, buf, buflen) + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + int i; + unsigned long insn_value; + const CGEN_INSN_LIST *insn_list; + + switch (buflen) + { + case 8: + insn_value = buf[0]; + break; + case 16: + insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); + break; + case 32: + insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); + break; + default: + abort (); + } + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + struct cgen_fields fields; + int length; + +#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ + /* Supported by this cpu? */ + if (! m32r_cgen_insn_supported (insn)) + continue; +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + if ((insn_value & syntax->mask) == syntax->value) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields); + if (length > 0) + { + (*CGEN_PRINT_FN (insn)) (info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +int +print_insn_m32r (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + char buffer[CGEN_MAX_INSN_SIZE]; + int status, length; + static int initialized = 0; + static int current_mach = 0; + static int current_big_p = 0; + int mach = info->mach; + int big_p = info->endian == BFD_ENDIAN_BIG; + + /* If we haven't initialized yet, or if we've switched cpu's, initialize. */ + if (!initialized || mach != current_mach || big_p != current_big_p) + { + initialized = 1; + current_mach = mach; + current_big_p = big_p; + m32r_cgen_init_dis (mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); + } + + /* Read enough of the insn so we can look it up in the hash lists. */ + + status = (*info->read_memory_func) (pc, buffer, CGEN_BASE_INSN_SIZE, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible, try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE); + if (length) + return length; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return CGEN_DEFAULT_INSN_SIZE; +} diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c new file mode 100644 index 00000000000..9e1cc88b61a --- /dev/null +++ b/opcodes/m32r-opc.c @@ -0,0 +1,977 @@ +/* CGEN support code for m32r. + +This file is machine generated. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + + +#include "config.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "m32r-opc.h" + +struct cgen_keyword_entry m32r_cgen_opval_mach_entries[] = { + { "m32r", 0 }, + { "test", 1 } +}; + +struct cgen_keyword m32r_cgen_opval_mach = { + & m32r_cgen_opval_mach_entries[0], + 2 +}; + +struct cgen_keyword_entry m32r_cgen_opval_h_gr_entries[] = { + { "fp", 13 }, + { "lr", 14 }, + { "sp", 15 }, + { "r0", 0 }, + { "r1", 1 }, + { "r2", 2 }, + { "r3", 3 }, + { "r4", 4 }, + { "r5", 5 }, + { "r6", 6 }, + { "r7", 7 }, + { "r8", 8 }, + { "r9", 9 }, + { "r10", 10 }, + { "r11", 11 }, + { "r12", 12 }, + { "r13", 13 }, + { "r14", 14 }, + { "r15", 15 } +}; + +struct cgen_keyword m32r_cgen_opval_h_gr = { + & m32r_cgen_opval_h_gr_entries[0], + 19 +}; + +struct cgen_keyword_entry m32r_cgen_opval_h_cr_entries[] = { + { "psw", 0 }, + { "cbr", 1 }, + { "spi", 2 }, + { "spu", 3 }, + { "bpc", 6 }, + { "cr0", 0 }, + { "cr1", 1 }, + { "cr2", 2 }, + { "cr3", 3 }, + { "cr4", 4 }, + { "cr5", 5 }, + { "cr6", 6 } +}; + +struct cgen_keyword m32r_cgen_opval_h_cr = { + & m32r_cgen_opval_h_cr_entries[0], + 12 +}; + + +static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = { + { & m32r_cgen_hw_entries[1], "pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr }, + { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr }, + { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 } +}; + + +const struct cgen_operand m32r_cgen_operand_table[CGEN_NUM_OPERANDS] = +{ +/* sr: source register */ + { "sr", 12, 4, { 0, 0|(1<f_r2 = *valuep; + break; + case 1 : + fields->f_r1 = *valuep; + break; + case 2 : + fields->f_r1 = *valuep; + break; + case 3 : + fields->f_r2 = *valuep; + break; + case 4 : + fields->f_r2 = *valuep; + break; + case 5 : + fields->f_r1 = *valuep; + break; + case 6 : + fields->f_simm8 = *valuep; + break; + case 7 : + fields->f_simm16 = *valuep; + break; + case 8 : + fields->f_uimm4 = *valuep; + break; + case 9 : + fields->f_uimm5 = *valuep; + break; + case 10 : + fields->f_uimm16 = *valuep; + break; + case 11 : + fields->f_hi16 = *valuep; + break; + case 12 : + fields->f_simm16 = *valuep; + break; + case 13 : + fields->f_uimm16 = *valuep; + break; + case 14 : + fields->f_uimm24 = *valuep; + break; + case 15 : + fields->f_disp8 = *valuep; + break; + case 16 : + fields->f_disp16 = *valuep; + break; + case 17 : + fields->f_disp24 = *valuep; + break; + + default : + fprintf (stderr, "Unrecognized field %d while setting operand.\n", + opindex); + abort (); + } +} + +/* Main entry point for getting values from cgen_fields. */ + +CGEN_INLINE long +m32r_cgen_get_operand (opindex, fields) + int opindex; + const struct cgen_fields *fields; +{ + long value; + + switch (opindex) + { + case 0 : + value = fields->f_r2; + break; + case 1 : + value = fields->f_r1; + break; + case 2 : + value = fields->f_r1; + break; + case 3 : + value = fields->f_r2; + break; + case 4 : + value = fields->f_r2; + break; + case 5 : + value = fields->f_r1; + break; + case 6 : + value = fields->f_simm8; + break; + case 7 : + value = fields->f_simm16; + break; + case 8 : + value = fields->f_uimm4; + break; + case 9 : + value = fields->f_uimm5; + break; + case 10 : + value = fields->f_uimm16; + break; + case 11 : + value = fields->f_hi16; + break; + case 12 : + value = fields->f_simm16; + break; + case 13 : + value = fields->f_uimm16; + break; + case 14 : + value = fields->f_uimm24; + break; + case 15 : + value = fields->f_disp8; + break; + case 16 : + value = fields->f_disp16; + break; + case 17 : + value = fields->f_disp24; + break; + + default : + fprintf (stderr, "Unrecognized field %d while getting operand.\n", + opindex); + abort (); + } + + return value; +} + -- 2.30.2